Modular Semiconductor Packaging With Interposer Vias for 3D Integration

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Solution Overview

Problem

The limited substrate layout budget in semiconductor devices hinders the integration of multiple semiconductor dice in a single package, necessitating an improved packaging technology to reduce substrate occupation and enhance performance.

Innovation Solution

A modular semiconductor device is developed, comprising an encapsulant layer with conductive vias and an interposer layer that allows for efficient electrical coupling between semiconductor components, enabling a compact and scalable design by stacking multiple semiconductor devices on a base component with interlayer connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If more semiconductor dice are integrated in a single package, then the functionality and performance of the electronic product are improved, but the substrate layout area required increases

Engineering Contradiction:

Improveintegration of semiconductor diceVSAvoidsubstrate layout area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent transitions from a two-dimensional substrate layout to a three-dimensional stacked architecture. Multiple semiconductor dice are vertically stacked and interconnected through conductive vias and interlayer connection regions, enabling more components to be integrated without increasing the substrate footprint. This vertical stacking approach directly addresses the contradiction by moving integration from the planar domain to the vertical domain.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where semiconductor dice are stacked one upon another, with each layer containing components and interconnection structures. The encapsulant layer with conductive vias penetrates through multiple layers, creating a nested configuration where smaller components are positioned within the vertical space occupied by larger structures, thereby maximizing space utilization.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Area of stationary object

If the substrate layout area is reduced, then the device size is minimized, but the complexity of interlayer connections increases

Engineering Contradiction:

Improvesubstrate layout areaVSAvoidinterlayer connection structure

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent divides the interconnection system into distinct functional segments: substrate interconnection structures at the base, encapsulant layer with conductive vias for vertical connections, and interlayer connection regions for horizontal routing. This segmentation allows each layer to be optimized independently, reducing overall complexity despite the three-dimensional architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The encapsulant layer with embedded conductive vias serves as an intermediary structure that facilitates vertical electrical connections between stacked semiconductor dice. This intermediary approach simplifies the connection process by providing pre-formed conductive pathways, reducing the complexity of direct wire bonding or other interlayer connection methods.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Area of stationary object

If multiple semiconductor components are stacked vertically, then the substrate occupation is reduced, but the heat management challenge increases

Engineering Contradiction:

Improvesubstrate occupationVSAvoidheat management

Core Design Contradiction:

Area of stationary objectVSTemperature

Solution Approach 1:

The encapsulant layer acts as a thermal intermediary, providing thermal pathways between stacked semiconductor components and the substrate heat sink. The conductive vias embedded in the encapsulant layer serve dual purposes: electrical interconnection and thermal conduction, facilitating heat dissipation from upper layers to the substrate without requiring additional thermal management structures.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20230411263A1Modular semiconductor devices and electronic devices incorporating the same

Publication Date: 2023.12.21 STATS CHIPPAC LTD

AI summary

A modular semiconductor device comprises: an encapsulant layer with an encapsulant bottom surface and an encapsulant top surface, wherein the encapsulant layer comprises a component region and an interlayer connection region; wherein the semiconductor component comprises a component conductive pattern exposed from the encapsulant bottom surface; an interlayer connection array disposed within the interlayer connection region, wherein the interlayer connection array comprises one or more conductive vias each extending between the encapsulant bottom surface and the encapsulant top surface; and an interposer layer laminated on the encapsulant layer and having an interposer bottom surface and an interposer top surface, wherein the interposer top surface is in contact with the encapsulant bottom surface; wherein the interposer layer comprises an interposer conductive pattern on the interposer bottom surface, and an interposer interconnection structure electrically coupled to the component conductive pattern, the interposer conductive pattern and the one or more conductive vias.