Modular Periphery IP Tiles for FPGA Shoreline Scalability

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Solution Overview

Problem

Integrated circuit devices, such as FPGAs, face limitations in scalability and performance due to a restricted shoreline area, which restricts the number and type of periphery IP that can be included, leading to design compromises and reduced device performance for various product variations.

Innovation Solution

The solution involves disaggregating periphery IP from the main programmable fabric and modularizing them into independent periphery IP tiles, allowing for independent design and fabrication. These tiles communicate with the programmable fabric via a silicon interposer and stitched direct communication, enabling modular interfacing and improving scalability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If periphery IP are placed on the shoreline of the programmable fabric, then device functionality is provided, but the restricted shoreline area limits the number and type of periphery IP that can be included

Engineering Contradiction:

ImprovescalabilityVSAvoidshoreline area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The periphery IP are segmented into separate modular tiles that can be independently designed, fabricated, and selected. Each periphery IP type (e.g., DDR memory, transceivers, I/O blocks) is divided into discrete tiles that can be independently placed around the programmable fabric, eliminating the constraint of continuous shoreline area and enabling greater scalability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A silicon interposer is introduced as an intermediary component between the programmable fabric and the periphery IP tiles. The interposer provides standardized interfaces and routing, allowing periphery IP tiles to be connected to the fabric without directly consuming shoreline area. This mediator enables flexible placement and connection of periphery tiles while maintaining signal integrity and reducing design complexity.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If periphery IP are disaggregated into modular tiles, then scalability and customization are improved, but device complexity increases due to multiple independent components

Engineering Contradiction:

Improveproduct variation scalabilityVSAvoidnumber of independent tiles

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The silicon interposer is designed with universal, standardized interfaces that can accommodate multiple types of periphery IP tiles. The same interposer architecture and interface standards can be used across different device variations, allowing a single interposer design to support various combinations of periphery tiles. This universality reduces the complexity increase by providing a common platform for diverse tile implementations.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If periphery IP are included in the main programmable fabric, then routing circuitry is consumed, but device performance is reduced for certain product variations

Engineering Contradiction:

Improvedevice performanceVSAvoidrouting circuitry consumption

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Periphery IP are extracted from the main programmable fabric and placed on separate modular tiles. This extraction eliminates the need for these high-bandwidth components to consume routing circuitry within the fabric, preserving routing resources for logic operations. The periphery tiles connect to the fabric through the silicon interposer, which handles the high-speed interfacing externally, thereby improving device performance for product variations that require extensive routing resources.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS20250077753A1Modular periphery tile for integrated circuit device

Publication Date: 2025.03.06 ALTERA CORP

AI summary

Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.