Modular PHY Synchronization Across Wide Memory Interfaces
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Solution Overview
Problem
Current memory interfaces face challenges in achieving high-bandwidth synchronization across multiple IO modules, particularly in configuring different clock domains without propagating asynchronous signals, and in supporting various memory protocols with flexible initialization and training.
Innovation Solution
A modular physical layer (PHY) architecture with an array of synchronous groups of IO modules, each receiving a delayed synchronous pulse signal, managed by a manager circuit that remaps interconnect redundancy and handles outbound and inbound control and data streams, allowing for configuration in a different clock domain and supporting various memory protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple IO modules are used to increase bandwidth, then data transmission capacity is improved, but synchronization difficulty increases due to clock domain propagation issues
Solution Approach 1:
The interface is divided into multiple synchronous groups, where each group contains a subset of IO modules that share a common delayed synchronous pulse signal. This segmentation allows independent timing control for different module subsets, enabling high-bandwidth operation without propagating asynchronous signals across the entire interface.
Solution Approach 2:
A chain of synchronous delay circuits acts as an intermediary between the clock domain and individual IO modules. These delay circuits receive a master clock signal and generate appropriately delayed synchronous pulse signals for each synchronous group, mediating the timing relationships without requiring direct asynchronous signal propagation between modules.
2Adaptability or versatility
If fixed interface configuration is used to simplify design, then device complexity is reduced, but adaptability to different memory protocols decreases
Solution Approach 1:
The interface configuration is made dynamic through programmable control circuits that can be configured at initialization to support different memory protocols. Parameters such as clock domain settings, synchronous group assignments, and IO module functions can be adjusted based on the required protocol, allowing a single device to adapt to multiple protocols without hardware changes.
3Adaptability or versatility
If asynchronous signals are propagated across clock domains, then flexibility in clock domain configuration is improved, but signal integrity and timing closure deteriorate
Solution Approach 1:
Instead of propagating asynchronous signals, the system uses periodic synchronous pulse signals generated by the synchronous delay circuits. Each synchronous group receives regularly timed pulses that are synchronized to their specific clock domain, ensuring predictable timing behavior and reliable timing closure while still allowing different clock domain configurations.
Data Source
AI summary
One embodiment relates to an integrated circuit with an array of modular physical layer (PHY) slice circuits that are configured into multiple synchronous groups. Each synchronous group receives a delayed synchronous pulse signal provided by a chain of synchronous delay circuits. Another embodiment relates to an array of modular PHY slice circuits, each of which includes a manager circuit that manages the modular PHY slice circuit, a remap circuit that remaps interconnect redundancy, and an input-output module that provides outbound control and data streams and receives inbound control and data streams.