Modular Semiconductor Package Interconnects for Higher PoP Density
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher integration density and component density in semiconductor devices, particularly in Package-on-Package (PoP) technology, where smaller and more creative packaging techniques are needed to enhance functionality and reduce footprint.
Innovation Solution
The use of multiple interconnect components attached to core substrates, incorporating electrical routing and integrated devices, allows for improved yield and reduced manufacturing costs through smaller interconnect structures that can be tested before packaging, enabling design flexibility and performance improvements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional semiconductor packaging methods are used, then manufacturing simplicity is maintained, but integration density and component density cannot be sufficiently increased
Solution Approach 1:
The patent implements Package-on-Package (PoP) technology where a first semiconductor package is stacked on top of a second semiconductor package, with each package containing multiple interconnect structures. This nesting approach allows multiple functional units to be integrated in a vertical configuration, significantly increasing integration density and component density while maintaining a compact footprint on the printed circuit board.
Solution Approach 2:
The patent divides the semiconductor package into multiple discrete interconnect structures (first, second, third, and fourth interconnect structures) that can be independently formed, tested, and assembled. Each interconnect structure contains conductive lines, vias, and semiconductor devices that can be separately manufactured and quality-checked before final packaging, enabling modular manufacturing and improved yield.
2Productivity
If smaller interconnect structures are used to increase units per wafer, then manufacturing cost is reduced, but testing and quality assurance become more difficult
Solution Approach 1:
The patent performs testing on interconnect structures at multiple stages before final packaging. Known good interconnect structures are identified and selected through preliminary testing, ensuring that only qualified structures are assembled into the final package. This preliminary quality assurance approach maintains high productivity while effectively managing testing challenges for miniaturized structures.
3Adaptability or versatility
If multiple interconnect structures are integrated in a single package, then functionality is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the multi-functional package into multiple independent interconnect structures that can be manufactured and tested separately. Each interconnect structure contains its own conductive lines, vias, and semiconductor devices, allowing for standardized manufacturing processes and reduced alignment complexity while maintaining enhanced functionality through modular integration.
Data Source
AI summary
A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.