Modular Prescaler Clock Divider for 50% Duty Cycle Outputs
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Solution Overview
Problem
Existing digital clock signal frequency divider circuits with prescaler architecture struggle to produce a 50% duty cycle for all lower frequency output signals, which is desirable for high-speed circuits like dual data rate circuits.
Innovation Solution
A programmable digital clock signal frequency divider module and modular digital clock signal frequency divider circuit with a prescaler architecture that uses primary and secondary divider modules, including latch circuits and a multiplexer, to process input clock signals and generate output signals with adjustable periods and duty cycles, ensuring a 50% duty cycle for the module clock output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a prescaler architecture frequency divider circuit is used, then the circuit can convert input clock signals to multiple lower frequency output signals, but the output signals cannot maintain a 50% duty cycle for all frequency divisions
Solution Approach 1:
The frequency divider is divided into multiple independent modules, each handling specific division ratios. The first module handles divisions of 2, 3, or 4 while the second module handles divisions of 2 or 3. This segmentation allows each module to be optimized for maintaining 50% duty cycle at its specific division ratios, resolving the contradiction between versatility and duty cycle accuracy.
Solution Approach 2:
The invention uses programmable control signals to dynamically configure the behavior of each frequency divider module. The control signals enable or disable specific feedback paths and latch circuits based on the desired division ratio, allowing the circuit to adaptively maintain 50% duty cycle across different frequency division operations.
2Device complexity
If traditional frequency divider circuits are used, then the circuit structure is simple, but long delay loops are required as feedback which increases circuit complexity and reduces speed
Solution Approach 1:
The invention extracts and eliminates the long delay loop feedback mechanism from the circuit. Instead of using traditional feedback paths that require long delay loops, the patent employs synchronous latch circuits controlled by programmable signals, thereby removing the speed-limiting element while maintaining the frequency division function.
Solution Approach 2:
The patent replaces the mechanical delay loop feedback system with a digital logic-based synchronous control system. The latch circuits are clocked by the input clock signal itself, eliminating the need for mechanical or analog delay elements and enabling higher operating speeds.
3Manufacturing precision
If programmable control is added to achieve 50% duty cycle for all outputs, then duty cycle accuracy improves, but device complexity increases
Solution Approach 1:
The patent designs universal frequency divider modules that can perform multiple division ratios (2, 3, or 4) using the same basic circuit structure. The programmable control signals enable a single module design to handle various division ratios while maintaining 50% duty cycle, reducing overall complexity compared to having separate dedicated circuits for each ratio.
Solution Approach 2:
The invention changes the control parameters (programmable enable signals) to alter the circuit behavior rather than changing the physical circuit structure. By manipulating control signals, the same hardware can achieve different division ratios with consistent 50% duty cycle output, avoiding the complexity of multiple specialized circuits.
Data Source
AI summary
A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module. Edges of the sequence of clock pulses trigger the divide by two latch, which results in a latch output clock signal with a 50% duty cycle at the output of the divide by two latch. Logic values at the tertiary input select either the sequence of clock pulses or the latch output clock signal to be a module clock output signal at the module clock output.