Modular PWB Vertical Interconnects for Fan-Out PoP Packaging
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Solution Overview
Problem
Current 3D packaging technologies for semiconductor devices, such as PoP, require laser drilling for vertical interconnects, which increases equipment costs, cycle time, and yield loss due to reduced control over interconnections and potential contamination of semiconductor dies.
Innovation Solution
The method involves forming modular vertical interconnect units using printed wiring board (PWB) technology, which eliminates the need for laser drilling by creating interconnect structures through a substrate and singulating them to form modular units around semiconductor dies, preventing contamination and improving control over interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If laser drilling is used to form vertical interconnects in PoP packaging, then vertical interconnections can be achieved, but equipment cost increases and manufacturing cycle time increases
Solution Approach 1:
The patent divides the substrate into multiple modular interconnect units, each containing pre-formed vertical interconnect structures. This segmentation allows the vertical interconnections to be created using standard PWB fabrication processes rather than requiring expensive laser drilling equipment for the entire package, thus reducing equipment costs while maintaining reliable vertical interconnections.
Solution Approach 2:
The vertical interconnect structures are formed in advance during the PWB fabrication process before the semiconductor dies are attached. This preliminary formation of interconnect structures eliminates the need for subsequent laser drilling operations, reducing both equipment costs and manufacturing cycle time while ensuring precise alignment and reliable connections.
2Reliability
If laser drilling is used to form vertical interconnects, then interconnections can be created, but manufacturing cycle time increases
Solution Approach 1:
The vertical interconnect structures are formed during the initial PWB fabrication process rather than being created later through laser drilling. This preliminary action consolidates multiple manufacturing steps into the standard PWB production flow, significantly reducing the overall manufacturing cycle time while ensuring high-quality vertical interconnections are achieved.
Solution Approach 2:
The patent combines the formation of vertical interconnect structures with the standard PWB fabrication process. By merging these operations into a single integrated manufacturing flow rather than performing them sequentially (PWB fabrication followed by laser drilling), the manufacturing cycle time is reduced while maintaining reliable vertical interconnections.
3Reliability
If laser drilling is used for vertical interconnects, then interconnections can be formed, but control over interconnections is reduced and yield loss increases
Solution Approach 1:
By segmenting the substrate into modular interconnect units with pre-formed vertical structures, the patent achieves precise control over each interconnection's location, dimensions, and electrical properties during the PWB fabrication process. This segmentation allows for better manufacturing precision and higher yield compared to post-fabrication laser drilling, which has less control and higher variability.
4Reliability
If conductive materials are used for vertical interconnects, then electrical connections are achieved, but contamination of semiconductor dies occurs
Solution Approach 1:
The patent extracts the vertical interconnect structures from the final package assembly process and incorporates them into the PWB substrate itself during fabrication. This extraction eliminates the risk of conductive material contamination to semiconductor dies that would occur if laser drilling or other post-assembly processes were used, while still achieving reliable electrical interconnections through the PWB's controlled impedance traces and vias.
Data Source
AI summary
A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.