Modular Reduction Bit Segmentation for Lower DSP Usage
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Solution Overview
Problem
The computational performance of privacy-preserving computation, such as fully homomorphic encryption, degrades significantly compared to plaintext computation, necessitating improved hardware acceleration for practical applications.
Innovation Solution
A modular reduction operation method and apparatus that optimizes DSP resource usage by employing a modular reduction factor to split significant and redundant bits, allowing efficient modular reduction operations through bit shifting and subtraction, reducing the need for DSP units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional modular reduction algorithms (Barrett modular reduction) are used, then modular reduction can be performed, but a large quantity of DSP units are needed, degrading computational performance
Solution Approach 1:
The patent segments the modular reduction factor into significant bits and redundant bits. The significant bits are further divided into non-overlapping groups, allowing the reduction operation to be performed using fewer DSP units by processing bit groups rather than individual bits, thus reducing the quantity of DSP units needed while maintaining computational performance
Solution Approach 2:
The patent uses partial action by only processing the significant bits of the modular reduction factor through DSP units, while the redundant bits are handled through simpler operations. This partial processing approach reduces the quantity of DSP units required while still achieving accurate modular reduction results
2Productivity
If more DSP units are used to accelerate modular reduction operations, then service processing efficiency improves, but hardware resource consumption increases
Solution Approach 1:
By segmenting the modular reduction factor into significant and redundant bits, and further dividing significant bits into non-overlapping groups, the patent enables efficient modular reduction with fewer DSP units, thus improving service processing efficiency while reducing hardware resource consumption
Solution Approach 2:
The patent changes the parameter representation by introducing the concept of significant bits and redundant bits, and by adjusting the bit grouping strategy. This parameter change allows the same modular reduction operation to be performed with reduced hardware resources while maintaining or improving service processing efficiency
Data Source
AI summary
Embodiments of this specification provide modular reduction operation methods and apparatuses. In a service processing process based on secure computation, a modulo operation is performed on a given value x for a related modulus (prime number). In a related multiplication operation, processing such as shifting and addition can be performed on another multiplier based on redundant bits in one multiplier, and only consecutive non-overlapping bits in the one multiplier are used as significant bits to implement the multiplication operation with the another multiplier by using a DSP unit. This greatly reduces online usage of DSP units, and improves modular reduction efficiency.