Modular Sample-and-Hold Circuit for Lower Peak Sampling Current
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Solution Overview
Problem
Conventional sample-and-hold circuits experience high power consumption due to spiky current when sampling, especially in high-resolution systems, which increases settling error and requires additional circuitry to mitigate, degrading ADC linearity.
Innovation Solution
A sample-and-hold circuit design utilizing multiple parallel modules with staggered clock phases to reduce peak current and capacitor size, allowing for lower power consumption and improved linearity by distributing capacitance and activating switches in smaller steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single sampling capacitor with high capacitance value is used for high-resolution systems, then measurement precision is improved, but power consumption increases due to spiky current
Solution Approach 1:
The patent divides the single high-capacitance sampling capacitor into multiple smaller capacitors (first sampling capacitor and second sampling capacitor) connected in parallel. This segmentation allows the total capacitance to remain high for high-resolution sampling, while distributing the charging current across multiple capacitors reduces the peak current drawn from the driving circuit, thereby reducing power consumption and settling error.
2Measurement precision
If a single sampling capacitor with high capacitance value is used, then measurement precision is improved, but the circuit driving the sample-and-hold circuit experiences increased settling error
Solution Approach 1:
By segmenting the sampling capacitor into multiple parallel capacitors, the patent reduces the peak current demand on the driving amplifier. This allows the amplifier to settle to the required accuracy level before the sampling operation completes, thereby reducing settling error and improving the reliability of the conversion process while maintaining high resolution.
3Use of energy by moving object
If a low-pass filter is connected between the driving circuit and the sample-and-hold circuit to limit spiky current, then power consumption is reduced, but ADC linearity degrades due to additional input resistance
Solution Approach 1:
The patent achieves spiky current reduction through capacitor segmentation rather than by adding external filtering components. This internal approach eliminates the need for additional low-pass filters that would introduce input resistance and degrade ADC linearity, thereby maintaining both low power consumption and high linearity simultaneously.
4Use of energy by moving object
If a cascode switch is introduced to reduce peak current, then power consumption is reduced, but circuit area increases
Solution Approach 1:
The patent reduces peak current by segmenting the sampling capacitor into multiple parallel capacitors, which distributes the charging current. This approach achieves power reduction without requiring additional cascode switches or other current-limiting circuitry, thereby avoiding the area penalty associated with such components while still reducing power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces power consumption and area requirements, enhancing ADC linearity by minimizing spiky current and allowing for efficient integration with other circuitry.
Implementation Method 1
a first sample-and-hold module (302) including a first switch (306) and a first capacitor (308)
Data Source
AI summary
A sample-and-hold circuit is broken down into multiple parallel modules, and an output switch, where each module includes a switch and a capacitor. Each of the switches in the modules and the output switch are controlled by different phases of a clock signal. The sample-and-hold circuit receives an input signal and operates in sample and hold modes to generate a sampled output signal.