Modular SRAM with Gated Sub-Arrays for Low-Power Histogram Operations
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Solution Overview
Problem
The existing SRAM circuit for histogram data operations consumes high power due to its multi-cycle read-modify-write operation, particularly because the mathematical modify step occurs externally, causing data signal toggling on both output and input ports.
Innovation Solution
A modular memory architecture with sub-arrays for less significant and more significant bits, where a word line gating circuit selectively gates the passage of word line signals to the more significant bit sub-array based on a maximum value signal asserted by a detection circuit, allowing for efficient data modification within the SRAM circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the mathematical modify step occurs externally in the existing SRAM circuit, then the read-modify-write operation can be performed, but data signal toggling on both output and input ports causes high power consumption
Solution Approach 1:
The patent merges the data modification function into the memory circuit itself by integrating an adder circuit within the memory block. This allows the read-modify-write operation to be performed internally without external data toggling, combining the storage and arithmetic functions into a single integrated unit that reduces power consumption while maintaining operational capability
Solution Approach 2:
The patent introduces a gating circuit as an intermediary component that selectively controls word line signal transmission to different sub-arrays based on data content. This mediator enables conditional operation of memory sub-arrays, allowing the circuit to perform modifications only when necessary and reducing unnecessary signal toggling that consumes power
2Ease of operation
If the SRAM circuit uses a multi-cycle read-modify-write operation with external data modification, then the operation can be completed, but the multi-cycle process increases power consumption due to repeated signal toggling
Solution Approach 1:
The patent performs preliminary action by pre-charging bit lines and preparing the adder circuit before the actual read-modify-write operation. The gating circuit is also pre-configured based on the read data content, allowing the modification to proceed efficiently in a single cycle without repeated signal toggling that would consume additional energy
Solution Approach 2:
The patent uses periodic clock signals to control the timing of operations within the memory circuit. The gating circuit responds to clocked signals to enable or disable word line transmission based on data content, creating a rhythmic, controlled operation pattern that minimizes unnecessary signal transitions and reduces power consumption compared to uncontrolled multi-cycle operations
Data Source
AI summary
A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.