Modular SRAM Architecture for Single-Cycle Read-Modify-Write Power Reduction
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Solution Overview
Problem
Existing SRAM circuits require multi-cycle operations for read-modify-write operations, leading to higher power consumption due to data signal toggling, especially when the mathematical modify operation is performed externally.
Innovation Solution
A modular memory architecture is introduced, where the SRAM circuit is divided into a first sub-array for storing less significant bits and a second sub-array for storing more significant bits. Word line activation for the more significant sub-array is dependent on the data content read from the less significant sub-array during a single-cycle read-modify-write operation, with internal data modification circuits reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multi-cycle operations are used for read-modify-write operations, then external data calculation can be performed, but power consumption increases due to data signal toggling
Solution Approach 1:
The patent merges the data modification function into the memory array by integrating data modification circuits within the memory structure. This allows read-modify-write operations to be completed in a single cycle without requiring external calculation, thereby reducing power consumption from data signal toggling while maintaining full data calculation capability.
Solution Approach 2:
The memory array is segmented into multiple sub-arrays, each handling specific portions of data words. This segmentation enables selective activation of sub-arrays based on data content, reducing unnecessary data signal toggling and power consumption while maintaining the ability to perform external data calculations when needed.
2Use of energy by moving object
If a single-cycle read-modify-write operation is implemented, then power consumption is reduced, but the complexity of coordinating word line activation increases
Solution Approach 1:
The patent implements dynamic word line activation where the activation of more significant bit sub-array word lines depends on the data content read from the less significant bit sub-array. This dynamic coordination enables single-cycle read-modify-write operations by selectively activating only the necessary sub-arrays, reducing power consumption without requiring complex static control logic.
3Device complexity
If data modification is performed externally, then circuit simplicity is maintained, but operation time increases due to multi-cycle requirements
Solution Approach 1:
The patent performs preliminary actions by pre-charging bit lines and pre-positioning data modification circuits within the memory array before the actual read-modify-write operation. This allows the operation to complete in a single cycle rather than requiring multiple cycles for external data processing, significantly reducing operation time while maintaining circuit simplicity through the use of standard memory cell structures.
Data Source
AI summary
A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A first word line signal is applied to a selected one of the first word lines to read less significant bits from the first sub-array, and a mathematical operation is performed on the read less significant bits to produce modified less significant bits that are written back to the first sub-array. If the read less significant bits are saturated, a second word line signal is applied to a selected one of the second word lines to read more significant bits from the second sub-array, and a mathematical operation is performed on the read more significant bits to produce modified more significant bits that are written back to the second sub-array.