Modular Switch Buffer Optimization via Hash Table Reordering

The patent segments the reorder buffer into multiple smaller buffers, each dedicated to a specific flow or ordering domain. This segmentation allows parallel processing of different flows simultaneously, eliminating the head-of-line congestion that occurs when a single buffer must sequentially process all packets. Each segment can independently reorder packets for its assigned flow without blocking other flows, thereby maintaining packet ordering while improving overall throughput.

The patent implements dynamic buffer allocation where buffer resources are allocated based on actual traffic patterns and flow requirements rather than static pre-allocation. The system monitors packet disorder levels and dynamically adjusts buffer sizes and assignments, allowing memory resources to be efficiently utilized only when needed for reordering, thereby reducing overall memory allocation while maintaining reliable packet reordering capability.

The patent replaces the mechanical linked list management system with a more efficient data structure or indexing mechanism. Instead of using linked lists that require complex node management and pointer operations, the system employs direct addressing tables, hash tables, or array-based structures that provide O(1) access and eliminate the need for intricate list manipulation, thereby reducing management complexity while maintaining dynamic buffer size benefits.

The patent implements a nested buffer architecture where small, fast reorder buffers are nested within or integrated with larger, slower external packet buffers. The fast internal buffers handle time-critical reordering operations with minimal latency, while the larger external buffers provide additional capacity for long-term storage and overflow handling. This hierarchical nesting allows the system to achieve both high buffer capacity and fast access speeds by appropriately matching buffer types to operational requirements.