Modular Test Access Architecture for 3D Stacked ICs
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Solution Overview
Problem
Current test architectures for 3D stacked ICs interconnected by through-substrate vias (TSVs) face challenges in efficiently testing manufacturing defects, particularly in pre-bond die testing, due to limitations in existing test access mechanisms and the need for scalable, flexible, and cost-effective solutions that minimize substrate area and test length.
Innovation Solution
A modular test access architecture that includes die-level wrappers with dedicated probe pads, TestElevators for signal transportation, and a hierarchical Wrapper Instruction Register (WIR) chain, enabling pre-bond and post-bond testing with flexible scheduling and minimal additional area cost, while reusing existing design-for-test infrastructure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional test access architectures (IEEE 1149.1/1500) are used for 3D stacked ICs, then testing can be performed on individual dies or cores, but the test length and substrate area requirements increase significantly when scaling to multiple stack tiers
Solution Approach 1:
The test architecture is segmented into modular wrapper units, each associated with a specific die or core in the stack. Each wrapper unit independently manages test access to its associated die, allowing parallel test operations across multiple stack tiers without requiring centralized test control that would consume excessive substrate area.
Solution Approach 2:
The patent transitions from traditional 2D test access architectures to a 3D test access architecture that exploits the vertical dimension of stacked ICs. Test signals can propagate vertically through the stack via TSVs, enabling test access to multiple tiers simultaneously and reducing the lateral substrate area required for test infrastructure.
2Reliability
If dedicated test infrastructure is added to each die for comprehensive testing, then testing coverage improves, but the additional area cost and device complexity increase
Solution Approach 1:
The wrapper units are designed as universal, standardized components that can be instantiated on every die in the stack using the same design. This multi-functional approach allows a single wrapper unit design to handle various test operations (intra-die testing, inter-die interconnect testing, and stack-level testing) without requiring different test infrastructure on different dies, thereby reducing overall device complexity.
Solution Approach 2:
The test architecture employs a hierarchical nesting structure where wrapper units at the die level are nested within a stack-level test access mechanism. The wrapper units provide fine-grained control for individual dies, while the stack-level mechanism coordinates testing across multiple tiers, creating a nested hierarchy that achieves comprehensive coverage without linearly increasing complexity.
3Ease of operation
If test signals are routed through embedded IP cores to access inter-die interconnects, then testing can be performed, but correctness of the IP core functionality is assumed which may not be valid for defective cores
Solution Approach 1:
The wrapper units serve as intermediary components between the test access mechanism and the embedded IP cores. Instead of routing test signals directly through the IP cores, the wrapper units provide a dedicated test interface that can control and observe the inter-die interconnects independently of the IP core functionality. This allows testing to proceed even when IP cores are defective, as the wrapper units remain functional for test purposes.
4Adaptability or versatility
If flexible test scheduling is implemented to accommodate pre-bond and post-bond testing, then testing adaptability improves, but the control mechanism complexity increases
Solution Approach 1:
The test architecture implements dynamic reconfigurability through the wrapper units, which can be programmed via instruction registers to perform different test operations at different stages of the manufacturing process. The same physical hardware can be dynamically reconfigured for pre-bond testing (where dies are tested individually before stacking) or post-bond testing (where complete stacks are tested), providing flexibility without requiring separate dedicated hardware for each test mode.
Data Source
AI summary
A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.