Modulated Gate Driver for Display Signal Timing Compensation
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Solution Overview
Problem
In large display devices, signal delays and distortions in gate and data signals lead to unsynchronized input timings for pixels, resulting in image luminance degradation due to increased signal line lengths and positional deviations.
Innovation Solution
A display device with a gate driver that generates modulated gate-on and gate-off voltages by adding overshoot and undershoot voltages to basic voltages based on the gate clock signal, ensuring uniform gate signal distribution and compensating for signal delays, thereby maintaining synchronized input timings for data and gate signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the display panel size is increased, then the display area is improved, but signal delay and waveform distortion occur in gate lines and data lines
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the gate-on voltage level according to the position of the gate line. Specifically, gate-on voltages are set to different levels (first level for first gate lines, second level for second gate lines, third level for third gate lines) to compensate for signal delays caused by different line lengths. This positional parameter adjustment ensures uniform gate signal timing across the entire display panel while maintaining larger display area.
2Length of stationary object
If the gate line length is increased, then the display width is improved, but gate signal waveform distortion occurs at distant portions
Solution Approach 1:
The patent implements local quality by applying different gate-on voltage levels to different regions or positions of gate lines. Instead of using a uniform voltage level across all gate lines, the system assigns specific voltage levels (first, second, third levels) to different gate line positions to compensate for local signal delay variations. This localized voltage adjustment maintains gate signal waveform stability throughout the extended gate line length.
3Area of stationary object
If the data line length is increased, then the display area is improved, but data signal timing synchronization with gate signal deteriorates
Solution Approach 1:
The patent compensates for data signal timing delays by adjusting gate signal timing parameters based on positional information. The controller determines positional information of pixels and accordingly adjusts gate-on voltage levels and timing to ensure that data signals and gate signals are synchronized at each pixel location, even when data line lengths vary across the large display area.
Data Source
AI summary
A display panel includes a plurality of gate lines and a plurality of pixels disposed thereon, a gate driver which applies a gate signal to the gate lines, and a controller which controls the gate driver, where the controller includes a signal controller which generates a scanning start signal and a gate clock signal comprising a plurality of pulses, where the scanning start signal instructs to start a scanning of the gate signal, and a driving voltage modulator which generates a modulated gate-on voltage and a modulated gate-off voltage based on a basic gate-on voltage and a basic gate-off voltage, where the driving voltage modulator adds an overshoot voltage corresponding to a rising edge of a pulse of the gate clock signal to the basic gate-on voltage or adds an undershoot voltage corresponding to a falling edge of the pulse of the gate clock signal to the basic gate-off voltage.