Modulated FinFET Gate Structure for Leakage and Capacitance Control
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Solution Overview
Problem
As semiconductor devices scale down, challenges arise with increased leakage current between source/drain regions and gate structures, leading to device failure and reduced performance due to short channel effects and parasitic capacitances, which are exacerbated in gate-all-around (GAA) and fin field effect transistors (finFETs).
Innovation Solution
Implementing modulated gate structures with varying lengths in semiconductor devices, where a portion of the gate structure below the fin top surface is narrower than the portion above, achieved through controlled etching of a polysilicon layer and spacer formation, aligning source/drain regions to the spacer, and forming gate structures in the resulting space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate-all-around (GAA) and fin field effect transistors (finFETs) are used to scale down semiconductor devices, then storage capacity and processing speed are improved, but leakage current between source/drain regions and gate structures increases
Solution Approach 1:
The gate structure is designed with different widths at different vertical positions: a first width at the top portion and a second width at the bottom portion, where the second width is less than the first width. This local variation in gate dimensions reduces the overlap area between the gate and source/drain regions, thereby reducing parasitic capacitance and leakage current while maintaining the beneficial scaling effects of GAA and finFET structures.
2Quantity of substance
If device dimensions are scaled down to increase storage capacity, then device density is improved, but short channel effects and parasitic capacitances are exacerbated
Solution Approach 1:
The modulated gate structure implements local quality variation by having a narrower bottom portion and wider top portion. This configuration maintains high device density through vertical scaling while locally reducing the gate-source/drain overlap at critical interfaces, thereby mitigating parasitic capacitances and short channel effects that typically worsen with scaling.
Solution Approach 2:
The invention addresses two-dimensional scaling challenges by introducing a third dimensional variation in gate width along the vertical axis. This modulated gate structure varies the gate width in the vertical dimension, allowing density improvement through scaling while compensating for increased parasitic effects through strategic width modulation at different heights.
Data Source
AI summary
The present disclosure describes a semiconductor device with modulated gate structures and a method for forming the same. The method includes forming a fin structure, depositing a polysilicon layer over the fin structure, and forming a photoresist mask layer on the polysilicon layer. The method further includes etching, with a first etching condition, the polysilicon layer not covered by the photoresist mask layer and above a top surface of the fin structure. The method further includes etching, with a second etching condition, the polysilicon layer not covered by the photoresist mask layer and below the top surface of the fin structure, where the etched polysilicon layer below the top surface of the fin structure is narrower than the etched polysilicon layer above the top surface of the fin structure. The method further includes removing the etched polysilicon layer to form a space and forming a gate structure in the space.