Modulated Thickness I/O Structures for Semiconductor Warpage Compensation

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Solution Overview

Problem

The increasing number of I/Os on semiconductor chips and their corresponding package substrates leads to shrinking dimensions, resulting in smaller mechanically tolerances and issues with die and substrate warpage during the solder attach process, which can cause faulty connections due to improper reflow of solder balls, leading to high resistance or open circuits.

Innovation Solution

Modulating the thickness of pads and solder balls on the package substrate by varying the electric current density during electroplating, with thicker pads and balls at outer regions and thinner ones at inner regions to compensate for warpage, ensuring proper contact and connection between die and substrate I/Os.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of I/Os on semiconductor chips is increased, then the performance and functionality of the package is improved, but the dimensions of individual I/O structures shrink and mechanical tolerances become tighter, leading to warpage issues

Engineering Contradiction:
Improvenumber of I/OsVSAvoidmechanical tolerances
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by varying the thickness of pads and solder balls at different locations on the substrate. Specifically, pads and solder balls at outer regions are made thicker than those at inner regions, creating location-specific structural properties that compensate for warpage effects and maintain manufacturing precision across the entire package despite increased I/O density

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If uniform thickness pads and solder balls are used across the substrate, then the manufacturing process is simpler, but warpage causes improper contact and faulty connections at outer regions

Engineering Contradiction:
Improveuniform thickness fabricationVSAvoidconnection reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent implements local quality by making pad and solder ball thickness location-dependent rather than uniform. Outer region pads and solder balls are fabricated with greater thickness to compensate for warpage-induced gaps, ensuring reliable connections across the entire substrate while maintaining a controlled fabrication process through systematic variation

Inventive Principle:
Principle #3Local quality

3Reliability

If thicker pads and solder balls are used throughout, then connection reliability is improved, but the overall package size increases and mechanical tolerances are compromised

Engineering Contradiction:
Improveconnection reliabilityVSAvoidpackage dimensions
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent applies local quality by selectively increasing pad and solder ball thickness only at outer regions where warpage causes connection problems, while maintaining standard thickness at inner regions. This localized approach ensures connection reliability where needed without unnecessarily increasing overall package dimensions

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures that all I/Os are properly formed and connected, reducing the risk of short or open circuits by maintaining appropriate mechanical contact and reflowed solder connections across the die and substrate interface, even with pronounced warpage.

Implementation Method 1

Modulating the thickness of pads and solder balls on the package substrate by varying the electric current density during electroplating

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS20230086649A1Semiconductor Chip Package Having Internal I/O Structures With Modulated Thickness To Compensate For Die/Substrate Warpage
Publication Date: 2023.03.23 INTEL CORP
  • US20230086649A1 patent drawing
  • US20230086649A1 patent drawing
  • US20230086649A1 patent drawing

AI summary

An apparatus is described. The apparatus includes I/O structures having pads and solder balls to couple with a semiconductor chip, wherein, a first subset of pads and/or solder balls of the pads and solder balls that approach the semiconductor chip during coupling of the semiconductor chip to the I/O structures are thinner than a second subset of pads and/or solder balls of the pads and solder balls that move away from the semiconductor chip during the coupling of the semiconductor chip to the I/O structures.