Modulated Signal Traces for IC Package Substrates
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Solution Overview
Problem
High-speed digital signals face challenges during integrated-circuit chip miniaturization as they require increased speed, and existing technologies struggle to effectively manage signal trace capacitance and insertion loss in compact chip designs.
Innovation Solution
The implementation of modulated signal-trace configurations within integrated-circuit wiring, where the trace form factor is modified by varying its width and height to reduce capacitance and stabilize insertion loss, using ground-stitching vias to shield the landing pad and extend the trace cantilever fashion over a recess in the package material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the chip size is reduced during miniaturization, then the integration density is improved, but the signal trace capacitance increases and insertion loss worsens
Solution Approach 1:
The patent applies local quality by creating a void region specifically beneath the signal trace to reduce capacitance in that localized area. The void is positioned only where needed - under the trace - while leaving other areas of the chip unaffected. This localized modification reduces the dielectric material surrounding the trace, thereby reducing capacitance and insertion loss without requiring overall chip size increase.
Solution Approach 2:
The patent introduces a vertical dimension solution by creating a void region beneath the trace in the Z-direction (depth). Instead of modifying the trace horizontally, the solution adds a third dimension - a subsurface void space - that reduces capacitance by removing dielectric material from below the trace, thus addressing insertion loss through dimensional expansion rather than planar modification.
2Volume of moving object
If the chip size is reduced during miniaturization, then the integration density is improved, but the signal trace capacitance increases
Solution Approach 1:
The patent applies the extraction principle by removing dielectric material from beneath the signal trace to create a void region. This extraction of material directly reduces the capacitance-forming dielectric substance surrounding the trace, thereby lowering signal trace capacitance without adding any compensating elements that would increase chip size.
3Object-affected harmful factors
If ground-stitching vias are used to shield the landing pad, then the electromagnetic interference is reduced, but the device complexity increases
Solution Approach 1:
The patent applies multi-functionality by designing the void region to serve multiple purposes simultaneously: it reduces capacitance and insertion loss by removing dielectric material, provides electromagnetic shielding by preventing field coupling to underlying structures, and acts as a reference plane for impedance control. This single structural feature accomplishes what would traditionally require multiple separate elements, thereby reducing overall device complexity.
Data Source
AI summary
Disclosed embodiments include a signal trace in an integrated-circuit device package substrate. Portions of the signal traces, suspend a landing pad in a recess, and a portion of the suspended signal trace is form-factor modulated that is different in cross-section area than other portions of the suspended signal trace.