Modulating Germanium Percentage in SiGe Stressors for MOS Devices

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Solution Overview

Problem

Current Metal-Oxide Semiconductor (MOS) devices face limitations in performance enhancement due to challenges in modulating the channel region's stress and germanium percentage, which affect carrier mobility and source-to-drain resistance.

Innovation Solution

The process involves forming a gate stack on a semiconductor substrate, growing SiGe stressors in recesses to apply compressive stress, and using epitaxial growth to create regions with varying germanium percentages, followed by silicidation to reduce source/drain resistance and enhance carrier mobility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If SiGe stressors are grown in recesses to apply compressive stress to the channel region, then carrier mobility is improved, but source-to-drain resistance increases

Engineering Contradiction:
Improvecarrier mobilityVSAvoidsource-to-drain resistance
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent applies different germanium percentages at different locations: higher germanium content (30-70%) in the stressor regions adjacent to the channel to maximize compressive stress and carrier mobility, while maintaining lower germanium content in other regions to control source-to-drain resistance. This spatial variation in material composition resolves the contradiction by optimizing each region for its specific function.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent modulates the germanium percentage parameter across different regions of the device. By changing the germanium concentration from 0% in pure silicon regions to 30-70% in stressor regions, the patent simultaneously achieves the desired compressive stress for high carrier mobility while controlling the overall resistance characteristics through parameter optimization.

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If germanium percentage is increased in source and drain regions, then source-to-drain resistance is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvesource-to-drain resistanceVSAvoidmanufacturing complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent divides the source and drain regions into multiple segments with different germanium percentages. The first source/drain regions have a first germanium percentage while the second source/drain regions have a second germanium percentage. This segmentation allows independent optimization of each region's electrical characteristics while using standardized fabrication processes for each segment, thereby managing manufacturing complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a compositional dimension by varying germanium percentage across different regions and depths. Instead of uniform composition, the patent creates a graded or stepped germanium distribution in the vertical and lateral dimensions, enabling fine-tuned control of source-to-drain resistance through compositional profiling rather than complex geometric structures.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces source-to-drain resistance and enhances carrier mobility by introducing stress and optimizing germanium distribution, thereby improving MOS device performance.

Implementation Method 1

Since SiGe has a lattice constant greater than that of silicon, it applies a compressive stress to the channel region

Methodology Applied
Scientific EffectLattice mismatch stress:

Implementation Method 2

epitaxial growth to create regions with varying germanium percentages

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 3

followed by silicidation to reduce source/drain resistance

Methodology Applied
Scientific EffectSilicidation:

Data Source

PatentUS10014411B2Modulating germanium percentage in MOS devices
Publication Date: 2018.07.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10014411B2 patent drawing
  • US10014411B2 patent drawing
  • US10014411B2 patent drawing

AI summary

An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.