Modulating Programming Voltage for Non-Volatile Memory Endurance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory cells in semiconductor devices face challenges in maintaining high endurance cycles without experiencing over-programming, which leads to increased threshold voltage distributions and bit errors, reducing read voltage margins and increasing power consumption.
Innovation Solution
Modulating the programming voltage applied to non-volatile memory cells over time based on the number of program/erase cycles and bit count ratios, adjusting the voltage reduction frequency and interval to minimize over-programming and maintain lower read voltage margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If programming voltage is maintained at high levels to ensure reliable programming, then programming reliability is improved, but over-programming occurs leading to increased threshold voltage distributions and bit errors
Solution Approach 1:
The patent applies dynamics by making the programming voltage adjustable and adaptive rather than fixed. The system dynamically modulates the programming voltage based on the number of program/erase cycles experienced by the memory block, transitioning from static high voltage to dynamic adaptive voltage to prevent over-programming while maintaining programming reliability.
Solution Approach 2:
The patent changes the programming voltage parameter over time based on cycle count. By monitoring the number of program/erase cycles and adjusting the programming voltage accordingly (reducing it after certain cycle thresholds), the system prevents threshold voltage distribution widening while ensuring adequate programming at earlier cycles.
2Manufacturing precision
If programming voltage is increased to reduce bit errors, then programming accuracy is improved, but power consumption increases
Solution Approach 1:
The patent optimizes the programming voltage parameter to achieve the minimum necessary voltage for accurate programming at each cycle stage. By reducing voltage after certain cycle thresholds are reached, the system maintains programming accuracy when needed while minimizing power consumption during later cycles where lower voltages suffice.
Solution Approach 2:
The patent applies partial action by using high programming voltage only when necessary (early cycles) and reducing it later when the memory block has already experienced some cycling. This avoids excessive voltage application that would increase power consumption unnecessarily while still achieving adequate programming accuracy.
3Reliability
If read voltage margin is increased to reduce bit errors, then reading reliability is improved, but power consumption increases
Solution Approach 1:
By dynamically adjusting the programming voltage based on cycle count, the patent prevents threshold voltage distribution widening that would otherwise require increased read voltage margins. This maintains reading reliability while avoiding the power consumption penalty associated with larger read voltage margins.
4Manufacturing precision
If programming voltage is reduced to prevent over-programming, then threshold voltage distribution is maintained, but programming reliability may deteriorate
Solution Approach 1:
The patent applies preliminary action by using higher programming voltage early in the memory block's life (low cycle counts) when the threshold voltage distribution is still tight and can accommodate higher voltages. This ensures reliable programming before the distribution widens, and only reduces voltage later when preliminary conditioning has already occurred.
Solution Approach 2:
The system dynamically adjusts programming voltage based on real-time cycle count monitoring. By transitioning from high voltage to lower voltage as cycles accumulate, the system maintains programming reliability when needed while preventing over-programming-induced distribution widening at later stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances cycling endurance, reduces bit errors, and lowers power consumption by adaptively adjusting programming voltages as the number of program/erase cycles increases, maintaining a stable read voltage margin.
Implementation Method 1
The amount of charge on the floating gate is typically controlled using Fowler-Nordheim (F-N) tunneling or hot-electron injection
Implementation Method 2
the control circuit may determine a first bit count ratio for a first threshold voltage distribution in response to detection that the memory block has exceeded the first program/erase cycle threshold
Data Source
AI summary
Systems and methods for increasing cycling endurance and minimizing over programming of non-volatile memory cells by modulating the programming voltage applied to the non-volatile memory cells over time as the number of program/erase cycles increases are described. A bit count ratio based on bit counts within two threshold voltage zones may be used to determine the amount of voltage reduction in the programming voltage applied during subsequent programming operations. For example, if the bit count ratio is between 0.02 and 0.05, then the reduction in the programming voltage may be 100 mV; if the bit count ratio is between 0.05 and 0.10, then the reduction in the programming voltage may be 200 mV. The modulation (e.g., the reduction) of the programming voltage may be performed at varying cycle intervals depending on the total number of program/erase cycles for a memory block and/or the bit count ratio.