Module-Level ECC Circuit Pools Memory Data
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Solution Overview
Problem
Conventional semiconductor memory devices face limitations in error correction capabilities due to the limited number of parity bits, which restricts the detection and correction of errors, especially as memory processes shrink and data fidelity requirements become more stringent.
Innovation Solution
Implementing a module-level error correction code (ECC) circuit that pools data and parity bits from multiple memory devices, allowing for increased error detection and correction capabilities without increasing the number of parity bits, by using additional memory input/output terminals, multilevel signaling, and subdividing pooled data and parity to reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory devices use limited parity bits for error correction, then the device complexity remains low, but the error detection and correction capabilities are insufficient
Solution Approach 1:
The patent combines data and parity bits from multiple memory devices into a pooled structure, allowing a single ECC circuit to perform error correction across the entire module. This merging approach increases error detection and correction capabilities without requiring separate ECC circuits for each memory device, thus improving reliability while controlling device complexity.
Solution Approach 2:
The ECC circuit is designed to perform multiple functions: it can correct errors in data bits, verify parity bits, and operate at both device and module levels. This multi-functionality allows the same circuit to handle various error correction scenarios, improving reliability without proportionally increasing device complexity.
2Reliability
If additional memory cells are used to increase parity bits for better error correction, then error detection and correction capabilities improve, but the manufacturing cost and device area increase
Solution Approach 1:
The patent merges resources across multiple memory devices by pooling their data and parity bits together. This allows the system to achieve enhanced error correction capabilities using the existing parity bits from multiple devices rather than adding more memory cells dedicated to parity storage, thus improving reliability without increasing the total number of memory cells.
Solution Approach 2:
The patent transitions from device-level error correction to module-level error correction, adding a new dimension to the error correction architecture. By pooling data and parity bits across multiple devices into a module-level structure, the system achieves better error correction without requiring additional memory cells within individual devices.
3Adaptability or versatility
If module-level ECC pooling is implemented across multiple memory devices, then error correction flexibility increases, but the data transmission time and latency increase
Solution Approach 1:
The patent segments the pooled data and parity bits into multiple portions that can be processed in parallel by the ECC circuit. This segmentation allows the error correction process to handle large amounts of data more efficiently, reducing the time penalty associated with module-level error correction while maintaining the flexibility benefits of pooling.
Solution Approach 2:
The patent performs preliminary organization of data and parity bits into pooled structures before error correction is needed. This preliminary action allows the ECC circuit to work with pre-organized data during error correction operations, reducing the processing time required when actual error correction is performed while maintaining the adaptability of module-level operations.
Data Source
AI summary
Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.