Module Reset Circuit for SoC Exception Handling
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Solution Overview
Problem
Existing SoC chip reset mechanisms face challenges in efficiently handling exceptional events due to unclear reset boundaries, leading to low exception handling efficiency and limited application scenarios.
Innovation Solution
A module reset circuit is introduced, comprising a signal receiving circuit, first and second signal generation circuits, and an operational circuit, which generates a module-based reset signal to reset exceptional timing sequence devices individually, reducing the number of modules reset and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global-based reset mechanism or clock domain-based reset mechanism is employed to reset timing sequence devices in the chip, then the entire chip can be reset to handle exceptional events, but the reset boundary becomes unclear and exception handling efficiency decreases
Solution Approach 1:
The patent divides the chip into multiple functional modules, each with its own reset control circuit. This segmentation allows independent reset of specific modules rather than resetting the entire chip, thereby maintaining clear reset boundaries and improving exception handling efficiency while preserving reliability.
2Reliability
If a global-based reset mechanism or clock domain-based reset mechanism is employed, then the chip can handle exceptional events, but the number of modules that need to be reset increases, resulting in low exception handling efficiency
Solution Approach 1:
The patent implements module-level reset control where each functional module has independent reset capability. This allows only the exceptional module to be reset rather than multiple modules, reducing the quantity of modules affected and improving exception handling efficiency while maintaining reliability.
Solution Approach 2:
The patent applies different reset strategies to different modules based on their specific needs. Each module has its own reset control circuit that can be independently activated, allowing precise control over which modules are reset, thereby minimizing the number of modules affected while ensuring reliable exception handling.
3Measurement precision
If a module-level reset mechanism is implemented to reset only exceptional modules, then exception handling precision is improved, but the device complexity increases due to additional reset control circuits
Solution Approach 1:
The patent divides the reset control functionality into distributed module-level reset control circuits, each responsible for a specific functional module. This segmentation achieves clear reset boundaries and precise exception handling while managing complexity through modular design, where each module's reset circuit is self-contained and standardized.
Data Source
AI summary
A signal receiving circuit receives a reset configuration signal from an exceptional timing sequence device in a functional module and outputs a trigger signal. A first signal generation circuit generates an idle signal based at least in part on the trigger signal. The idle signal is used to configure a shutdown signal which in turn is used to shut down a first clock signal of the exceptional timing sequence device and a second clock signal in a same clock domain as the first clock signal. A second signal generation circuit generates a reset enable signal based at least in part on the trigger signal. An operational circuit performs an operation based at least in part on the reset enable signal and generates a module-based reset signal based at least in part on an operation result. The module-based reset signal is used to reset the exceptional timing sequence device in the functional module.