Modulo Calculation Hardware Logic Using Bit String Grouping
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Solution Overview
Problem
Existing hardware logic for calculating the modulus of an n-bit number with respect to an unsigned m-bit constant is either small in terms of area but slow, or faster but larger in area, failing to optimize for both speed and area effectively, especially when the constant is not a power of two.
Innovation Solution
The implementation of hardware logic using a series of addition units, each comprising binary adders, that groups input bits into strings, multiplies them by corresponding coefficients, and adds the results to efficiently reduce the range of intermediate values, allowing for flexible design optimizing for speed or area based on the specific application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If iterative division implementation is used to calculate modulus, then the calculation can be performed, but the hardware area increases and speed decreases
Solution Approach 1:
The input number is divided into multiple groups of bits, where each group is processed separately through addition units. This segmentation allows parallel processing of different bit groups, significantly improving calculation speed while maintaining accuracy. The modulus calculation is broken down into smaller intermediate calculations that can be performed concurrently.
Solution Approach 2:
The patent transforms the modulus calculation problem by changing the parameters of intermediate values. By carefully controlling the range and bit-width of intermediate results through specific addition operations, the patent reduces the complexity of subsequent calculations. The intermediate values are kept within a manageable range that optimizes both speed and hardware resource usage.
2Productivity
If lookup tables and multiplexers are used for constant b, then calculation speed improves, but hardware area increases
Solution Approach 1:
The patent employs a dynamic approach where the structure of addition units can be adaptively configured based on the specific values of input numbers and the constant b. Rather than using a fixed large lookup table, the addition units dynamically process different bit groupings and intermediate value ranges, achieving high speed with reduced hardware area through flexible, adaptive computation paths.
3Productivity
If bits are grouped into strings with multiplication by coefficients, then intermediate value range is reduced, but device complexity increases
Solution Approach 1:
Different groups of bits are processed with different coefficients tailored to their specific positions and weights. Each addition unit is optimized for its specific function in the overall calculation chain, with coefficients selected to minimize the range of intermediate values for that particular bit group. This localized optimization reduces overall complexity while maintaining high efficiency.
Data Source
AI summary
Hardware logic is arranged to efficiently perform modulo calculation with respect to a constant value b. The hardware logic comprises a series of addition units (each comprising a plurality of binary adders). A first stage addition unit in the series groups bits from an input number into a number of strings, multiplies each string by a corresponding coefficient using adders and left-shifting and adds the resulting strings together to generate an intermediate value which, in most examples, has a smaller range of possible values than the input number. The series of addition units also includes a second stage addition unit and/or a final stage addition unit. A second stage addition unit uses similar methods to generate an updated intermediate value in a pre-defined terminating range. A final stage addition unit generates a final result from the final intermediate result output by an immediately previous addition unit in the series.