Modulo Calculation Using GF(2) Polynomial Rings
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Solution Overview
Problem
Existing hardware logic for calculating the modulus of an n-bit number with respect to an unsigned m-bit constant either requires a large area for fast computation or is slow due to the use of additions and subtractions, which are inefficient in terms of hardware implementation.
Innovation Solution
The implementation of modulo calculation using a finite polynomial ring with polynomial coefficients in GF(2), where the generator polynomial has a repeat period that is a multiple of the constant b, allowing for efficient binary multiplication within the ring to reduce hardware size and computation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If iterative division or lookup tables are used for modulo calculation, then computation speed is improved, but hardware area increases
Solution Approach 1:
The patent transforms the modulo calculation problem by changing the parameter space from integer arithmetic to polynomial arithmetic over GF(2). By representing numbers as polynomials and performing multiplication instead of division, the computation achieves both speed and compactness. The key transformation is mapping the modulo operation to polynomial multiplication modulo a generator polynomial, which eliminates the need for large lookup tables while maintaining fast computation.
Solution Approach 2:
The patent replaces the mechanical division operation with polynomial multiplication in a finite field. Instead of using iterative division circuits or large lookup tables, the system uses polynomial multiplication followed by reduction modulo a generator polynomial. This substitution leverages the algebraic structure of GF(2)[x] to achieve efficient hardware implementation with reduced area and comparable or improved speed.
2Area of stationary object
If additions and subtractions are used in modulo calculation, then hardware area is reduced, but computation time increases
Solution Approach 1:
The patent changes the computational parameters from sequential addition/subtraction operations to parallel polynomial multiplication operations. By working in the polynomial ring over GF(2), the system can perform multiple bit-level operations simultaneously, reducing computation time while maintaining compact hardware. The polynomial multiplication structure naturally enables parallel processing that eliminates the sequential delays inherent in addition-based approaches.
3Area of stationary object
If polynomial multiplication in GF(2) is used, then hardware logic size is reduced, but implementation complexity increases
Solution Approach 1:
The patent introduces an intermediary polynomial representation system that bridges the gap between simple hardware operations and complex modulo calculation. By using polynomials over GF(2) as an intermediate representation, the system can perform calculations using simple XOR and AND operations (which are easy to implement in hardware) while achieving the functionality of complex modulo arithmetic. The generator polynomial acts as a mediator that enables reduction without requiring complex division circuits.
Data Source
AI summary
Hardware logic arranged to perform modulo calculation with respect to a constant value b is described. The modulo calculation is based on a finite polynomial ring with polynomial coefficients in GF(2). This ring is generated using a generator polynomial which has a repeat period (or cycle length) which is a multiple of b. The hardware logic comprises an encoding block which maps an input number into a plurality of encoded values within the ring and a decoding block which maps an output number back from the ring into binary. A multiplication block which comprises a tree of multipliers (e.g. a binary tree) takes the encoded values and multiplies groups (e.g. pairs) of them together within the ring to generate intermediate values. Groups (e.g. pairs) of these intermediate values are then iteratively multiplied together within the ring until there is only one intermediate value generated which is the output number.