Modulo Arithmetic Circuit With Fixed Shifts for Faster Memory Encryption
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Solution Overview
Problem
Existing modulo operation circuits for encryption schemes, such as those used in post-quantum cryptography, require large circuit areas and consume significant time due to the high number of variations in shift amounts, which is not efficient for applications like memory systems.
Innovation Solution
A modulo arithmetic device with reduced variations in shift amounts by correlating bit lengths of the divisor with fixed shift operations, using a first shift circuit to perform a shift operation based on the bit length of the divisor and a second shift circuit with a fixed shift amount of 32 bits, reducing circuit area and operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional modulo operation circuits are used with high variations in shift amounts, then the circuit can handle various encryption schemes, but the circuit area becomes large and operation time increases
Solution Approach 1:
The patent applies parameter changes by correlating the shift amount with the bit length of the divisor q. Instead of using variable shift amounts for different encryption schemes, the patent establishes a fixed relationship where the shift amount is determined by the bit length of q, reducing the number of variations in shift amounts while maintaining compatibility with various encryption schemes.
Solution Approach 2:
The patent applies local quality by making the shift operation specific to the bit length of the divisor. The shift amount is locally adapted to match the bit length of q, creating a tailored operation for each specific divisor size while maintaining a unified circuit structure that reduces overall complexity.
2Adaptability or versatility
If conventional modulo operation circuits are used with high variations in shift amounts, then the circuit can handle various encryption schemes, but the operation time becomes long
Solution Approach 1:
The patent reduces operation time by changing the parameter relationship between shift amount and divisor bit length. By establishing a direct correlation where shift amount equals the bit length of q, the patent eliminates the need for multiple shift operations with varying amounts, thereby reducing the total operation time while maintaining scheme compatibility.
Solution Approach 2:
The patent extracts the shift operation from being a variable, scheme-dependent parameter to a fixed operation based solely on the bit length of the divisor. This extraction simplifies the operation sequence and reduces the time required for modulo operations across different encryption schemes.
3Speed
If the number of variations in shift amounts is reduced, then the circuit area becomes smaller and operation speed increases, but the adaptability to different encryption schemes may be limited
Solution Approach 1:
The patent resolves this contradiction by changing the parameter relationship to correlate shift amount with divisor bit length. This allows the circuit to maintain high operation speed with reduced shift amount variations while preserving adaptability, as the shift operation automatically adapts to different schemes through its dependency on the divisor's bit length rather than requiring multiple fixed shift amounts.
Data Source
AI summary
According to a modulo arithmetic device of one embodiment, a first intermediate value is acquired by shifting right a dividend by a shift amount w correlated with a bit length of a divisor. The shift amount w takes a value not more than the bit length of the divisor. A second intermediate value is acquired by multiplying the first intermediate value by a value m. A third intermediate value is acquired by shifting right the second intermediate value by a shift amount (2k−w). The parameter k takes a value equal to or larger than the bit length of the divisor. A fourth intermediate value is acquired by multiplying the third intermediate value by the divisor. A fifth intermediate value is acquired by subtracting the fourth intermediate value from the dividend. A remainder is acquired by subtracting a value n-times the divisor from the fifth intermediate value.