Modulo K Calculation Circuitry Using Segmented Partial Operands
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Solution Overview
Problem
Existing data processing apparatuses require complex logic and extensive resources to calculate modulo k values, making them time-consuming and inefficient.
Innovation Solution
The apparatus splits the input data value into partial operands and uses a series of combination stages to calculate modulo k values, reducing the number of operations required by combining groups of partial operands, thereby simplifying the logic and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional division/multiplication logic is used to calculate modulo k values, then calculation accuracy is maintained, but circuit complexity and computation time increase significantly
Solution Approach 1:
The input data value is segmented into multiple partial operands (e.g., 8 partial operands for an 8-bit value). Each partial operand is processed independently to generate a corresponding modulo k value, which are then combined through addition and modulo operations to produce the final result. This segmentation eliminates the need for complex division logic while maintaining calculation accuracy.
2Speed
If extensive lookup tables are used to store precomputed modulo values, then calculation speed improves, but memory resources and circuit area increase
Solution Approach 1:
Instead of storing a complete lookup table for all possible input values, the method segments the input into partial operands and only stores/computes modulo values for these smaller components. This reduces the lookup table size from requiring entries for all 2^N possible N-bit values to only requiring computations for the segmented partial operands, significantly reducing circuit area while maintaining fast computation through the combination stages.
Solution Approach 2:
The method pre-computes modulo k values for partial operands (such as powers of 2) and stores these in small lookup tables or hardwires them into the circuit. These precomputed values are then combined using addition and modulo operations to obtain the final result, avoiding the need for large lookup tables that would store precomputed values for all possible input combinations.
3Ease of manufacture
If repeated subtraction methods are used to compute modulo k, then implementation simplicity is maintained, but computation time increases
Solution Approach 1:
The input value is divided into partial operands, and the modulo operation is applied to each segment independently. The results are then combined through a series of addition and modulo operations in combination stages. This approach maintains implementation simplicity by using basic arithmetic operations while significantly reducing computation time compared to repeated subtraction of the entire input value.
Solution Approach 2:
The method pre-computes modulo k values for partial operands (such as powers of 2) and stores these precomputed values in lookup tables or hardwires them into the circuit. During operation, these precomputed values are retrieved and combined through addition and modulo operations, eliminating the need for repeated subtraction during the actual computation phase.
4Measurement precision
If complex division logic is implemented to ensure accurate modulo k calculation, then calculation precision is maintained, but the number of logic gates and circuit area increase
Solution Approach 1:
The input data value is divided into multiple partial operands (e.g., 8 partial operands for an 8-bit value). Each partial operand is processed independently to generate a corresponding modulo k value. These values are then combined through addition and modulo operations in combination stages to produce the final result. This segmentation reduces the number of logic gates required compared to implementing full division logic, as each segment can be processed with simpler operations.
Data Source
AI summary
There is provided a method and an apparatus for calculating an output modulo k value of an input data value. The apparatus is provided with input data value analysis circuitry to consider the input data value as a plurality of partial operands, and to determine a plurality of modulo k values corresponding to the plurality of partial operands. The apparatus is provided with modulo k calculation circuitry comprising plural combination stages to replace one or more groups of input modulo k values with one or more combined modulo k values. The plural combination stages comprise a first combination stage to receive the plurality of modulo k values as inputs and to output an intermediate reduced plurality of modulo k values, and one or more further combination stages to sequentially combine one or more groups of the intermediate reduced plurality of modulo k values to generate the output modulo k value.