High Performance Modulo Multiplication via Wallace Tree Feedback
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current modulo multiplication techniques are not optimized for high-frequency timing and result in significant area and performance impacts, particularly in applications like cryptography and security management.
Innovation Solution
The proposed method employs a high-performance modulo multiplication technique using a primary Wallace tree to obtain and sum partial products, feeding back results for subsequent limb multiplication, and utilizing a secondary Wallace tree for residual computations to achieve efficient modulo multiplication with minimal area impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional modulo multiplication techniques are used, then the multiplication can be completed, but the timing is not optimized for high-frequency operation and the area occupied is significant
Solution Approach 1:
The patent divides the multiplication process into multiple limbs, where each limb processes a portion of the operands. The multiplication is segmented such that partial products are generated and accumulated across different limbs, allowing the circuit to operate at higher frequencies by reducing the critical path delay within each limb while maintaining the overall multiplication functionality.
2Area of stationary object
If the multiplication process is split into limbs to reduce area, then the circuit area is reduced, but the number of cycles per multiplication increases
Solution Approach 1:
The patent implements a continuous accumulation mechanism where partial products from each limb are immediately added to the running total rather than waiting for complete limb processing. This continuous action allows the circuit to pipeline the multiplication operations, reducing the total number of cycles required while maintaining the area-efficient limb structure.
Solution Approach 2:
The patent uses feedback mechanisms where the accumulated partial products are fed back into the multiplication process for subsequent limbs. This feedback loop enables the circuit to reuse the same hardware resources across multiple limbs, reducing the overall multiplication time while maintaining area efficiency through resource sharing.
3Area of stationary object
If hardware for one limb is reused for subsequent limbs, then the area is reduced, but the timing complexity increases
Solution Approach 1:
The patent designs the limb hardware to be universal and multi-functional, where the same multiplication and addition circuits are used across all limbs. This universal design simplifies the timing analysis because the same hardware behavior is repeated predictably across limbs, reducing timing complexity despite the iterative reuse of hardware resources.
Data Source
AI summary
Embodiments herein disclose high performance modulo multiplication methods performed by circuitry of an electronic device. The method includes obtaining and summing partial products to obtain a partial multiplication result using a primary Wallace tree. The partial multiplication result is fed back in a next cycle for subsequent limb multiplication associated with the primary Wallace tree. The obtaining and summing of partial products and feeding back operations are repeated until all limbs associated with the primary Wallace tree are completed. A residual computation of a partial multiplication result associated with a final limb of the primary Wallace tree is then performed, to obtain a multiplication result using a secondary Wallace tree, where the final limb stores the partial multiplication result of a last iteration.