Modulo Operation Generator for Cache Memory Slice Distribution
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Solution Overview
Problem
Modulo operations involving a divisor that is not a power of two are complex and time-consuming, leading to reduced performance in cache memory systems, as they require multiple loops and repeated subtraction processes, which increase processing time and delay data storage in cache memory.
Innovation Solution
A computer-implemented method and system that perform modulo operations by executing a first set of summations, accessing correction values through a lookup table, and adjusting sums to generate a result efficiently, regardless of the dividend value, using an accumulation circuit, a lookup and correction circuit, and a test and correct circuit, specifically designed for Mersenne and Fermat number divisors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If modulo operations are performed with a divisor that is not a power of two, then the cache memory can distribute data items among non-power-of-two slices, but the processing time increases significantly due to multiple loops and repeated subtraction
Solution Approach 1:
The patent transforms the divisor into a Mersenne number (2^n - 1) to enable efficient modulo operations. By changing the parameter of the divisor to fit the Mersenne form, the complex repeated subtraction process is replaced with simple bitwise operations and addition, reducing processing time while maintaining the ability to handle non-power-of-two slice configurations
Solution Approach 2:
The patent replaces the mechanical repeated subtraction process with a mathematical transformation approach. Instead of iteratively subtracting the divisor from the dividend until the result is less than the divisor, the invention uses the property of Mersenne numbers to compute the modulo operation through bitwise NOT and addition operations, eliminating the need for loops
2Measurement precision
If traditional modulo operation methods are used with non-power-of-two divisors, then accurate residue values are obtained, but the number of processing steps increases leading to reduced cache memory performance
Solution Approach 1:
The patent changes the divisor parameter to a Mersenne number form (2^n - 1), which enables the modulo operation to be computed using bitwise operations rather than repeated subtraction. This parameter change maintains exact residue value computation while dramatically reducing the number of processing steps required
Solution Approach 2:
The patent performs preliminary transformation of the dividend and divisor into a form suitable for efficient computation. By representing the dividend in a specific format and using the Mersenne property, the necessary corrections are pre-calculated and applied in a single step rather than through iterative processes
Data Source
AI summary
Various embodiments include a modulo operation generator associated with a cache memory in a computer-based system. The modulo operation generator generates a first sum by performing an addition and/or a subtraction function on an input address. A first portion of the first sum is applied to a lookup table that generates a correction value. The correction value is then added to a second portion of the first sum to generate a second sum. The second sum is adjusted, as needed, to be less than the divisor. The adjusted second sum forms a residue value that identifies a cache memory slice in which the input data value corresponding to the input address is stored. By generating the residue value in this manner, the cache memory efficiently distributes input data values among the slices in a cache memory even when the number of slices is not a power of two.