Modulo Phase/Frequency Detector for Low-Complexity PLL Sensing

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Solution Overview

Problem

Existing phase/frequency detectors in digital phase locked loops face challenges with high complexity, power consumption, and sensitivity to external interference, particularly when dealing with high input frequencies and timing inaccuracies.

Innovation Solution

A phase/frequency detector comprising a modulo counter and a modulo integrator that generates a phase error word without the need for a differentiator, allowing for reduced complexity and power consumption by using modulo operations to limit the range of counter, integrator, and phase error words.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a fully synchronous counter with a differentiator is used as a frequency detector, then frequency detection capability is achieved, but device complexity and power consumption increase

Engineering Contradiction:
Improvefrequency detection accuracyVSAvoiddetector complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts and removes the differentiator component from the frequency detector architecture. By using a modulo counter without a differentiator, the system achieves frequency detection capability while reducing device complexity and power consumption, directly addressing the technical contradiction between measurement precision and device complexity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the operational parameters of the counter by using modulo arithmetic with a predetermined modulus value. This parameter change allows the counter to function as both a phase detector and frequency detector without requiring additional differentiating circuitry, thereby reducing complexity while maintaining detection accuracy

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If a modulo counter with predetermined word length is used, then device complexity is reduced, but phase detection accuracy may be limited

Engineering Contradiction:
Improvedetector complexityVSAvoidphase detection accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent implements dynamic phase wrapping using modulo arithmetic. The phase error word dynamically wraps around according to the predetermined modulus, allowing the system to maintain accurate phase detection over extended ranges without increasing word length or complexity. This dynamic approach resolves the contradiction between reduced complexity and maintained precision

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If a time-to-digital converter (TDC) is added for finer phase quantization, then phase detection precision is improved, but device complexity increases

Engineering Contradiction:
Improvephase quantization precisionVSAvoiddetector complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent makes the modulo counter multi-functional by designing it to simultaneously perform phase detection, frequency detection, and fine quantization functions. The predetermined word length and modulus value enable the single counter structure to achieve functions that would traditionally require separate TDC and phase detector circuits, thereby improving precision without increasing complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7592874B2Phase/frequency detector, phase locked loop, method for phase/frequency detection and method for generating an oscillator signal
Publication Date: 2009.09.22 APPLE INC
  • US7592874B2 patent drawing
  • US7592874B2 patent drawing
  • US7592874B2 patent drawing

AI summary

A phase/frequency detector has a modulo counter for outputting a counter word with a predetermined word length depending on an oscillator signal. In addition, a modulo integrator for outputting an integrator word with the predetermined word length as a function of integration of a channel word is provided. The phase/frequency detector also has a difference element for outputting a phase error word with the predetermined word length as a function of a difference between the counter word and the integrator word.