Modulo-N Routing Circuits for Non-Power-of-Two Address Mapping
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Solution Overview
Problem
Existing computer systems face inefficiencies when dealing with resource topologies where the number of routing options is not a power of two, leading to issues such as 'holes' in the address space and aliasing, particularly when modifying existing designs to accommodate non-power-of-two options.
Innovation Solution
A routing circuit that utilizes mod-n and div-n operations on different portions of the request address to determine routing selections for dimensions with non-power-of-two options, avoiding aliasing by combining mod-n and div-n results to ensure unique mappings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If power-of-two routing options are used in resource topology, then address space utilization is simple and efficient, but the system cannot accommodate non-power-of-two routing options which limits adaptability
Solution Approach 1:
The address space is segmented into multiple dimensions, where each dimension can independently represent a routing option. This segmentation allows the system to handle non-power-of-two routing options in specific dimensions without affecting the overall address space structure, thereby achieving flexibility while maintaining simplicity.
Solution Approach 2:
The patent introduces the concept of multiple dimensions in the address space, where each dimension can have a different number of routing options. This dimensional approach allows the system to accommodate non-power-of-two routing options in specific dimensions while keeping other dimensions as traditional power-of-two structures, resolving the contradiction between adaptability and complexity.
2Adaptability or versatility
If non-power-of-two routing options are implemented, then routing flexibility is improved, but address space holes and aliasing issues occur
Solution Approach 1:
By segmenting the address space into multiple dimensions, the patent ensures that each dimension independently manages its routing options. This segmentation prevents address space holes and aliasing by ensuring that each dimension's routing options are properly aligned and accounted for, thereby maintaining reliability while achieving flexibility.
Solution Approach 2:
The multi-dimensional address space structure allows the system to represent non-power-of-two routing options in specific dimensions without creating address space holes or aliasing. Each dimension is carefully designed to ensure complete and unique mapping, thus maintaining address space completeness while achieving routing flexibility.
3Productivity
If traditional routing methods are used, then implementation is straightforward, but efficiency is reduced when dealing with non-power-of-two routing options
Solution Approach 1:
The routing circuit is segmented into multiple dimension-handling units, each responsible for a specific dimension's routing options. This segmentation allows efficient handling of non-power-of-two routing options in affected dimensions while maintaining traditional efficient routing in other dimensions, thereby improving overall routing efficiency without excessive complexity.
Solution Approach 2:
The patent implements a multi-dimensional routing approach where the routing circuit can efficiently handle different numbers of routing options in different dimensions. This dimensional approach optimizes routing efficiency for non-power-of-two options by treating them as distinct dimensions with specialized handling, rather than forcing them into traditional power-of-two structures.
Data Source
AI summary
A modulo-n circuit, where n is not a power of two. A modulo-n circuit is configured to determine a modulo-n value for each of equal sub-portions of the particular value, resulting in a current set of modulo-n results, then combine pairs of the current set of modulo-n results to obtain a new set of modulo-n results having a greater number of bits than previous modulo-n results, with the new set of modulo-n results becoming the current set of modulo-n results. The modulo-n circuit is further configured to repeatedly combine the current set of modulo-n results until the new set of modulo-n results has a single modulo-n result that is a final result of the modulo-n operation. Examples of the modulo-n circuit include a modulo-3 circuit and a modulo-15 circuit. Div-n circuits are also disclosed. The modulo-n and div-n circuits may be usable in a routing circuit