Multiple-Modulus Divider Control for Accurate PLL Frequency Switching
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Solution Overview
Problem
Existing multiple-modulus dividers in frequency synthesizers face issues with erroneous frequency outputs due to operation differences in dividers, particularly when switching between divisor integers, leading to failure in converging the phase-locked loop (PLL) and inaccurate frequency division.
Innovation Solution
A multiple-modulus divider comprising a divisor loader, a multiple-modulus dividing circuit, and a modulus controller, where the divisor loader downloads divisors during a division period, and the modulus controller ensures selected dividers operate in an open-loop state to maintain accurate frequency division across divisor switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If divisor extension logic is added to extend the operable divisor range, then the frequency range coverage is improved, but the system complexity increases and erroneous frequency outputs occur due to operation differences in dividers
Solution Approach 1:
The patent applies preliminary action by setting the modulus input signals of skipped dividers to a fixed value (0 or 1) in advance before the division operation. This ensures that when dividers are skipped due to divisor extension, they are already in the correct state to prevent erroneous frequency outputs, thereby maintaining reliability while extending the operable divisor range.
Solution Approach 2:
The patent applies local quality by treating different dividers differently based on their position in the cascade. Dividers that are skipped due to divisor extension are given a fixed modulus input signal, while active dividers receive dynamic modulus input signals. This localized differentiation ensures correct operation across the extended divisor range without affecting the entire system.
2Adaptability or versatility
If multiple dividers are used to extend the divisor range, then the operable divisor range is improved, but the system complexity increases due to additional control logic
Solution Approach 1:
The patent reduces control logic complexity by performing preliminary actions: setting modulus input signals of skipped dividers to fixed values in advance. This eliminates the need for complex real-time control logic to manage skipped dividers, as their states are predetermined, thereby simplifying the overall control architecture while maintaining extended divisor range capability.
3Adaptability or versatility
If dividers are skipped to achieve high divisor values, then the maximum divisor is improved, but erroneous frequency outputs occur due to incorrect loop states
Solution Approach 1:
The patent applies preliminary action by pre-setting the modulus input signals of dividers that will be skipped to achieve high divisor values. This ensures these dividers are in the correct loop state (open-loop or closed-loop) before the division operation begins, preventing erroneous frequency outputs and ensuring measurement precision is maintained even at maximum divisor values.
Data Source
AI summary
A multiple-modulus divider and an associated control method are provided. The multiple-modulus divider includes a divisor loader, a multiple-modulus dividing circuit and a modulus controller. The divisor loader downloads a divisor when a download signal indicates a start of a division period. The multiple-modulus circuit includes a plurality of cascaded divisors, and provides an output frequency according to an input frequency and the divisor. The dividers respectively output a plurality of modulus output signals, and each is operable under either a close-loop state or an open-loop state. The modulus controller selects and controls one of the dividers according to the divisor, and ensures the selected divider is maintained at the open-loop state when the division period ends. The download signal corresponds to one of the modulus output signals.