Semiconductor Interconnect Structure With MOF Air Gaps for Low Capacitance
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to simultaneously achieve low metal resistivity (Rs) and low dielectric capacitance (C) as critical dimensions and pitch scale down, while preventing etch damage to low-k materials during patterning.
Innovation Solution
A semiconductor structure incorporating a metal-organic framework layer and an air gap is formed in concaves to reduce capacitance, using Zn, Sr, Pb, Mn, or Co-based organic network crystals, with the air gap occupying 50% to 80% of the concave and the framework layer occupying 20% to 50%, avoiding etch damage to low-k materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If critical dimension and pitch are scaled down, then device density is improved, but metal resistivity increases and dielectric capacitance increases
Solution Approach 1:
The patent introduces a porous low-k dielectric material with controlled porosity (20-50% air voids) to replace conventional dense dielectrics. This porous structure reduces the effective dielectric constant to below 2.5, thereby reducing capacitance and allowing for lower resistivity interconnects at scaled dimensions while maintaining device density
Solution Approach 2:
The patent employs composite interconnect structures combining copper or cobalt metal layers with porous low-k dielectric materials, and introduces novel materials such as metal-organic framework (MOF) layers and hexagonal boron nitride (h-BN) to create composite structures that simultaneously achieve low resistivity and low capacitance at nanoscale dimensions
2Manufacturing precision
If etching is used for patterning, then manufacturing precision is improved, but low-k material is damaged
Solution Approach 1:
The patent introduces etch-resistant capping layers (such as silicon nitride or silicon oxide) that serve as protective intermediaries between the etching process and the porous low-k dielectric material. These capping layers allow precise patterning to be performed while shielding the low-k material from etch damage, maintaining its integrity
Solution Approach 2:
The patent applies protective capping layers to the porous low-k dielectric material before the etching process begins. This preliminary protective action prevents etch damage from occurring during subsequent patterning steps, enabling high manufacturing precision without compromising the low-k material
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure maintains metal and dielectric integrity, reduces capacitance penalty, and prevents resistance penalty, offering better mechanical tolerance and thermal dissipation with ultra-low K values and low leakage current.
Implementation Method 1
The metal-organic framework layer has a plurality of holes. Some of the holes are connected with each other. Air is filled in the holes, so that the capacitance could be reduced.
Implementation Method 2
the air gap 122 and the dielectric capping layer 116, so the capacitance penalty could be lowered
Data Source
AI summary
A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure includes: forming a sacrificial layer in a concave in a metal layer; recessing the sacrificial layer; filling a metal-organic framework layer in the concave; and removing the sacrificial layer to form an air gap in the concave.