MOF Etch Mask Patterning for Fine-Pitch Integrated Circuits

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Solution Overview

Problem

The challenge of manufacturing integrated circuit (IC) devices with reduced component pitches while maintaining reliability and performance is not adequately addressed by existing technologies, particularly in the context of downscaling.

Innovation Solution

A method involving the formation of a metal-organic framework pattern using photolithography and vapor-phase precursors to create etch masks, which includes forming organic ligand and metal-containing monolayers to etch device layers, thereby enabling precise patterning and trench formation in insulating layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If component pitches are reduced to downscale IC devices, then operation speed and accuracy are improved, but manufacturing precision and reliability deteriorate

Engineering Contradiction:
Improveoperation speedVSAvoidmanufacturing precision
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The etch mask is segmented into multiple functional layers: a photoresist pattern layer providing initial patterning, and a metal-organic framework (MOF) pattern layer providing enhanced thickness and etch resistance. This segmentation allows each layer to specialize in different functions, enabling precise patterning at reduced pitches while maintaining sufficient mask durability during etching processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention uses a composite etch mask structure combining organic photoresist material with inorganic metal-organic framework material. The photoresist provides good lithographic properties for forming precise patterns, while the MOF layer adds thickness and chemical stability for robust etching protection. This composite approach resolves the contradiction between achieving fine pitch patterns and maintaining manufacturing precision.

Inventive Principle:
Principle #40Composite materials

2Area of stationary object

If component pitches are reduced to downscale IC devices, then device area is reduced, but reliability deteriorates

Engineering Contradiction:
Improvedevice areaVSAvoidreliability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The metal-organic framework pattern is formed in advance on the photoresist pattern before the etching process. This preliminary formation of the MOF layer ensures that the etch mask has sufficient thickness and chemical stability before exposure to etching conditions, preventing pattern degradation and ensuring reliable etching results even at reduced device areas and pitches.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dual-layer etch mask structure provides beforehand cushioning against etching damage. The thick MOF layer acts as a protective cushion that absorbs etching stress and prevents breakthrough to the underlying device layer, thereby maintaining pattern integrity and device reliability even when component pitches are reduced and features become more vulnerable.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Strength

If photoresist pattern thickness is increased to improve etch mask durability, then etch resistance is improved, but aspect ratio and patterning precision worsen

Engineering Contradiction:
Improveetch resistanceVSAvoidpatterning precision
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

Instead of increasing thickness in the vertical dimension alone, which would create high aspect ratio problems, the invention distributes the protective function across two dimensions: a thin photoresist layer for precise lateral patterning and a MOF layer for vertical thickness and etch resistance. This dimensional distribution allows achieving both high etch resistance and good patterning precision without suffering from excessive aspect ratio.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Different regions of the etch mask have different thicknesses and material compositions optimized for their specific functions. The photoresist layer is thin and optimized for lithographic resolution and pattern definition, while the MOF layer is thicker and optimized for etch resistance. This local quality optimization resolves the contradiction between etch resistance and patterning precision by allowing each layer to excel at its designated function.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the reduction of component pitches in IC devices, enhancing their reliability and performance by improving the precision and efficiency of the manufacturing process.

Implementation Method 1

forming an organic ligand monolayer by supplying a vapor-phase organic ligand precursor onto the substrate, the organic ligand monolayer being selectively bonded to a metal atom exposed on the substrate

Methodology Applied
Scientific EffectChemical adsorption: Chemisorption

Implementation Method 2

forming a metal-containing monolayer by supplying a vapor-phase metal precursor onto a resultant structure from the forming of the organic ligand monolayer, the metal-containing monolayer being selectively bonded to the organic ligand monolayer

Methodology Applied
Scientific EffectChemical adsorption: Chemisorption

Implementation Method 3

A photoresist pattern including a metal structure network is formed on a partial region of the device layer by using a photolithography process

Methodology Applied
Scientific EffectPhotolithography: Photopolymerisation

Data Source

PatentUS20250293029A1Method of manufacturing integrated circuit device using metal-organic framework
Publication Date: 2025.09.18 SAMSUNG ELECTRONICS CO LTD
  • US20250293029A1 patent drawing
  • US20250293029A1 patent drawing
  • US20250293029A1 patent drawing

AI summary

A method of manufacturing an integrated circuit device comprises forming a device layer on a substrate. A photoresist pattern comprising a metal structure network is formed on a partial region of the device layer using a photolithography process. A metal-organic framework pattern comprising at least one organic ligand layer and at least one metal-containing layer is formed on the photoresist pattern. The device layer may be etched by using the metal-organic framework pattern and the photoresist pattern as etch masks. The formation of the metal-organic framework pattern comprises forming an organic ligand monolayer, which is selectively bonded to metal atoms exposed on the substrate, by supplying a vapor-phase organic ligand precursor onto the substrate, and forming a metal-containing monolayer, which selectively bonded to the organic ligand monolayer, by supplying a vapor-phase metal precursor onto a resultant structure from the forming of the organic ligand monolayer.