MOF Insulating Layers for 3D Memory RC Delay Reduction
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Solution Overview
Problem
Three-dimensional memory devices face challenges with high dielectric constant insulating layers, such as silicon oxide and silicon nitride, which increase RC delay and are affected by electrical disturb and noise from neighboring memory cells, limiting the performance of word lines in program, erase, and read operations.
Innovation Solution
The implementation of metal-organic framework (MOF) insulating layers with a lower dielectric constant, grown inside backside recesses between word lines, reduces RC delay and improves insulating layer gap filling, using a method that involves forming a metal-containing precursor layer and reacting it with a vapor of a linking compound to create MOF material portions within interlayer cavities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional insulating layers (silicon oxide, silicon nitride) are used, then insulating properties are provided, but RC delay increases and noise interference occurs
Solution Approach 1:
The patent changes the dielectric constant parameter of the insulating layer material from traditional high-k materials (silicon oxide, silicon nitride) to low-k metal-organic framework materials. This parameter change directly reduces the RC delay while maintaining adequate insulating properties, resolving the contradiction between reliability and time loss.
Solution Approach 2:
The patent employs metal-organic framework composite materials that combine metal ions or clusters with organic linkers to create a novel insulating layer material. This composite structure achieves both low dielectric constant for reduced RC delay and sufficient insulating properties, simultaneously addressing both requirements.
2Reliability
If traditional insulating layers are used, then word line insulation is provided, but noise interference from neighboring memory cells increases
Solution Approach 1:
By changing the dielectric constant parameter to a lower value using metal-organic framework materials, the patent reduces the coupling between adjacent word lines, thereby minimizing noise interference from neighboring memory cells while maintaining proper word line insulation.
Solution Approach 2:
The patent converts the potential harmful effect of electrical coupling between adjacent word lines into a benefit by using low-k metal-organic framework materials that deliberately reduce this coupling, transforming what could be noise interference into improved electrical isolation and reduced crosstalk.
3Reliability
If insulating layers are formed between word lines, then electrical isolation is achieved, but gap filling between insulating layers is insufficient
Solution Approach 1:
The patent utilizes the porous nature of metal-organic framework materials to achieve excellent gap filling between word lines. The porous structure allows the material to conformally fill irregular spaces and cavities, ensuring complete electrical isolation while maintaining manufacturing precision.
Solution Approach 2:
The metal-organic framework composite material provides both the low dielectric constant for electrical isolation and a porous structure that enables superior gap filling capability, simultaneously resolving both the electrical isolation and manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MOF insulating layers significantly reduce word line RC delay, enhancing the speed and efficiency of program, erase, and read operations by providing improved insulating properties and reduced noise interference between memory cells.
Implementation Method 1
forming a metal-containing precursor layer in each of the interlayer cavities; and forming metal-organic framework (MOF) material portions by reacting the metal-containing precursor layer with a vapor of a linking compound
Data Source
AI summary
A three-dimensional memory device includes a vertically alternating stack of insulating layers and electrically conductive layers located over a top surface of a substrate and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a respective memory film and a respective vertical semiconductor channel, and each of the insulating layers contains a metal-organic framework (MOF) material portion. The MOF material portion has a low dielectric constant, and reduces RC coupling between the electrically conductive layers. An optional airgap may be located within the MOF material portion to further reduce the effective dielectric constant. Optionally, discrete charge storage regions or floating gates may be formed only at the levels of the electrically conductive layers to reduce program disturb and noise in the device.