Moiré Ferroelectric Gate Dielectric for Steep-Slope Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor chip feature sizes decrease, maintaining the operational reliability of transistor devices is challenging, particularly in developing technologies for the gate electrode layer, where conventional materials struggle to achieve efficient switching speeds and subthreshold swing characteristics.
Innovation Solution
A semiconductor device incorporating a ferroelectric structure with a moiré pattern formed by stacked two-dimensional material layers, which acts as a gate dielectric, enabling negative capacitance and reducing subthreshold swing, thereby improving switching speed and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional gate electrode materials are used in miniaturized transistor devices, then device size is reduced, but operational reliability and switching characteristics deteriorate
Solution Approach 1:
The gate dielectric structure uses a composite of multiple two-dimensional material layers (e.g., MoS2, WS2, WSe2, MoSe2) with different materials and thicknesses. This composite structure enables the system to achieve both miniaturization and maintained operational reliability through the synergistic effects of the layered materials, particularly utilizing ferroelectric properties for non-volatile memory functionality while keeping the device size reduced.
Solution Approach 2:
The patent changes the physical and chemical parameters of the gate dielectric by transitioning from conventional bulk materials to atomically thin two-dimensional materials with controlled layer numbers and thicknesses (e.g., 1-10 layers). This parameter change enables simultaneous achievement of small device size and reliable operation by exploiting quantum confinement effects and surface properties of 2D materials.
2Ease of manufacture
If conventional gate dielectric structures are used, then manufacturing is simpler, but subthreshold swing characteristics worsen (cannot achieve below 60 mV/decade)
Solution Approach 1:
The patent achieves precise subthreshold swing control (below 60 mV/decade) by changing the dielectric parameter - specifically introducing ferroelectric 2D material layers with switchable polarization. This enables ultra-steep slope characteristics that cannot be achieved with conventional paraelectric gate dielectrics, while the layer-by-layer growth method maintains manufacturing feasibility through sequential deposition processes.
Solution Approach 2:
The gate dielectric structure employs local quality differentiation by using specific 2D materials (e.g., MoS2 for 1-3 layers, WS2 for 1-5 layers, WSe2 for 1-3 layers, MoSe2 for 1-5 layers) with different ferroelectric properties at different positions in the stack. This localized material selection optimizes the overall subthreshold swing characteristics while maintaining manufacturing practicality.
3Length of moving object
If gate dielectric thickness is reduced for scaling, then device size decreases, but switching speed and on/off characteristics worsen
Solution Approach 1:
The patent uses a composite multilayer structure of different 2D materials (MoS2, WS2, WSe2, MoSe2) where each layer contributes different electrical and ferroelectric properties. This composite approach enables the ultra-thin gate dielectric (total thickness 1-10 layers) to maintain high switching speed and excellent on/off characteristics by combining the advantages of different materials - some providing high dielectric constant, others providing strong ferroelectric polarization for fast switching.
Solution Approach 2:
The patent transitions from three-dimensional bulk gate dielectric materials to two-dimensional atomic-layer materials, enabling thickness reduction to the atomic scale (1-10 layers) while maintaining or improving switching characteristics. The 2D nature of these materials provides high surface area to volume ratio and excellent interface quality, compensating for the reduced thickness and enabling fast switching despite ultra-thin dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ferroelectric structure with a moiré pattern effectively reduces subthreshold swing below 60 mV/decade, enhancing the on/off characteristics and switching speed of field effect transistors by controlling the thickness and ferroelectric properties of the gate dielectric layer.
Implementation Method 1
enabling negative capacitance and reducing subthreshold swing
Implementation Method 2
The ferroelectric structure including a plurality of two-dimensional material layers stacked to have a moiré pattern
Data Source
AI summary
A semiconductor device according to an embodiment includes a substrate having a channel region, a ferroelectric structure disposed over the channel region, and a gate electrode layer disposed on the ferroelectric structure. The ferroelectric structure includes a plurality of two-dimensional material layers disposed to have a moiré pattern.