Moiré Alignment and Vacuum Transfer for Sub-100 Nm Component Assembly
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Solution Overview
Problem
Current semiconductor fabrication methods are not suited for heterogeneous integration of disparate functional elements like electronics, photonic, and energy storage devices due to incompatible fabrication steps, and existing pick-and-place techniques lack nanoscale precision.
Innovation Solution
A method using vacuum-based pick-and-place with moiré based metrology for precise alignment and attachment of components onto a product substrate, achieving sub-100 nm placement precision through the use of a vacuum superstrate and adhesive techniques, including direct bonding and etching processes to create pillar-like structures for secure attachment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor fabrication methods are used for heterogeneous integration, then standard semiconductor packaging technology can be utilized, but incompatible fabrication steps prevent processing of diverse functional elements on a single substrate
Solution Approach 1:
The patent segments the heterogeneous integration process into separate fabrication stages. Different functional elements are fabricated on their respective source wafers using fabrication processes optimized for each material system, then transferred to a common product substrate. This avoids the need to process all incompatible fabrication steps on a single substrate while still achieving heterogeneous integration.
Solution Approach 2:
The patent introduces an intermediary transfer mechanism (vacuum-based pick-and-place system with moiré metrology) that acts as a mediator between the source wafers and the product substrate. This intermediary system enables the transfer of micrometer-sized components with nanometer-scale precision without requiring direct compatibility between the diverse fabrication processes.
2Manufacturing precision
If conventional pick-and-place techniques are used for heterogeneous integration, then assembly can be performed in short time scales, but placement precision is insufficient to achieve nanoscale alignment
Solution Approach 1:
The patent replaces conventional mechanical alignment and placement systems with a vacuum-based hold-down mechanism combined with moiré metrology. Instead of relying on complex mechanical positioning systems, the invention uses vacuum forces to hold components in place during transfer and employs optical moiré interference patterns to achieve nanometer-scale alignment precision.
Solution Approach 2:
The patent changes the operating parameters of the pick-and-place system by operating in a vacuum environment and using moiré interference patterns for alignment. This allows the system to achieve sub-100 nm placement precision while maintaining high-speed parallel assembly capabilities, effectively resolving the trade-off between precision and complexity.
3Productivity
If highly parallel pick-and-place is implemented, then assembly throughput is improved, but achieving arbitrary constituent distribution and nanometer-precise placement simultaneously becomes difficult
Solution Approach 1:
The patent performs preliminary alignment using moiré metrology before the actual placement operation. Alignment marks are pre-patterned on the source wafers and product substrate, allowing the system to calculate precise placement positions in advance. This preliminary alignment step enables highly parallel transfer operations to maintain nanometer-scale precision across all transferred components simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables highly parallel and precise assembly of components with sub-100 nm alignment, facilitating the integration of diverse functional elements on a single substrate, addressing the limitations of existing techniques by achieving nanoscale precision and efficient assembly processes.
Implementation Method 1
selectively picking one or more elements from a source wafer by a vacuum superstrate attached to the one or more elements
Implementation Method 2
placing the selectively picked one or more elements onto an adhesive on the product substrate with sub-100 nm placement precision
Implementation Method 3
etching the buried sacrificial layer using an etchant, where the etching of the buried sacrificial layer is timed in such a manner that pillar-like structures remain underneath the elements post-etch
Data Source
AI summary
A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise moiré alignment techniques resulting in highly accurate, parallel assembly of feedstocks.