Self-Aligned MOL Contacts via Selective Dielectric Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuit (IC) structures, forming gate contacts directly above the active region of field effect transistors (FETs) poses a risk of shorts with metal plugs, as existing methods require offsetting the gate contact to avoid shorts, limiting device size scaling.
Innovation Solution
The method involves forming a gate with a dielectric cap and sidewall spacer on the channel region, along with metal plugs having additional dielectric caps, using different selectively etchable dielectric materials to ensure self-aligned contact formation, reducing the risk of shorts between gate contacts and metal plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the gate contact is formed on a portion of the gate directly above the active region (CBoA), then device area is reduced enabling further scaling, but the risk of shorts between the gate contact and metal plugs increases
Solution Approach 1:
The patent introduces dielectric caps on metal plugs and dielectric sidewall spacers as intermediary protective layers between the gate contact and metal plugs. These intermediary structures prevent direct contact between conductive elements, eliminating the short risk while allowing the gate contact to be positioned directly above the active region for area scaling.
Solution Approach 2:
The dielectric caps are formed on the metal plugs before the gate contact is created. This preliminary action ensures that protective insulation is already in place before the gate contact formation process, preventing shorts from occurring during subsequent processing steps.
2Reliability
If the gate contact is offset from the active region to avoid shorts, then short risk is reduced, but device area increases limiting further scaling
Solution Approach 1:
The dielectric caps and sidewall spacers serve as intermediary protective structures that enable the gate contact to be positioned closer to the active region without causing shorts, thereby reducing the offset distance and minimizing device area while maintaining reliability.
3Manufacturing precision
If different selectively etchable dielectric materials are used for the dielectric cap, sidewall spacer, and additional dielectric caps, then self-aligned contact formation is enabled, but manufacturing complexity increases
Solution Approach 1:
The patent applies different dielectric materials with distinct etch selectivities to different local regions: the dielectric cap on the gate, the sidewall spacer on the gate sidewalls, and the additional dielectric caps on the metal plugs. This local differentiation enables selective etching processes that achieve self-aligned contact formation without requiring complex alignment steps.
Solution Approach 2:
The patent utilizes changes in dielectric material properties, specifically etch selectivity, to enable differential removal of dielectric layers. By selecting materials with different etch rates, the process achieves precise self-alignment where the gate contact and metal plug contacts are automatically positioned relative to each other through selective etching, simplifying the overall manufacturing process despite using multiple materials.
Data Source
AI summary
Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region of a field effect transistor (FET) and provide protection against shorts between the gate contact and metal plugs on source/drain regions and between the gate and source/drain contacts to the metal plugs. A gate with a dielectric cap and dielectric sidewall spacer is formed on a FET channel region. Metal plugs with additional dielectric caps are formed on the FET source/drain regions such that the dielectric sidewall spacer is between the gate and the metal plugs and between the dielectric cap and the additional dielectric caps. The dielectric cap, dielectric sidewall spacer and additional dielectric caps are different materials preselected to be selectively etchable, allowing for misalignment of a contact opening to the gate without risking exposure of any metal plugs and vice versa.