Dielectric Gate Cap Protection in MOL Contact Opening Etch
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Solution Overview
Problem
The fabrication of conductive contacts in integrated circuits during middle-of-the-line (MOL) interconnect processes can degrade the gate capping layer, leading to increased parasitic capacitance and reduced structural integrity due to etching processes that use fluorine-based etchants, causing damage to the gate capping layer and forming volatile by-products.
Innovation Solution
A selective etch and deposition process is used to form a dielectric protection layer along the top surface of the gate capping layer while concurrently etching the lower inter-level dielectric (ILD) layer, preventing damage to the gate capping layer and maintaining its structural integrity by reducing the formation of volatile by-products and rounding of corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fluorine-based etchants are used to etch the lower inter-level dielectric layer, then contact openings can be formed, but the gate capping layer is degraded and damaged
Solution Approach 1:
A dielectric protection layer is introduced as an intermediary between the fluorine-based etchant and the gate capping layer. This protection layer selectively prevents the etchant from damaging the gate capping layer while allowing the etching of the lower inter-level dielectric layer to proceed, thus resolving the contradiction between forming contact openings and preserving gate capping layer integrity
Solution Approach 2:
The dielectric protection layer is formed in advance before the etching process to preemptively protect the gate capping layer from the harmful effects of fluorine-based etchants. This preliminary protective action prevents the degradation and damage that would otherwise occur during contact opening formation
2Manufacturing precision
If fluorine-based etchants are used to etch the lower inter-level dielectric layer, then contact openings can be formed, but volatile by-products are generated
Solution Approach 1:
The dielectric protection layer acts as a barrier that prevents direct contact between the fluorine-based etchant and the gate capping layer, thereby preventing the formation of volatile by-products while still allowing the etching process to create the necessary contact openings
3Manufacturing precision
If fluorine-based etchants are used to etch the lower inter-level dielectric layer, then contact openings can be formed, but corner rounding occurs on the gate capping layer
Solution Approach 1:
The dielectric protection layer serves as a protective intermediary that prevents the fluorine-based etchant from attacking the corners of the gate capping layer during the contact opening formation process, thereby maintaining the sharp corners and proper shape of the gate capping layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance and enhances the structural integrity and performance of the integrated chip by protecting the gate capping layer during the formation of conductive contacts, thereby improving device reliability and performance.
Implementation Method 1
performing a selective etch and deposition process to selectively form a dielectric protection layer on a top surface of the gate capping layer
Implementation Method 2
performing a selective etch and deposition process to selectively form a dielectric protection layer on a top surface of the gate capping layer while forming a contact opening within the lower inter-level dielectric layer
Data Source
AI summary
In some embodiments, the present disclosure relates to a method for manufacturing an integrated chip. The method includes forming a transistor structure over a substrate. The transistor structure comprises a pair of source/drain regions and a gate electrode between the source/drain regions. A lower inter-level dielectric (ILD) layer is formed over the pair of source/drain regions and around the gate electrode. A gate capping layer is formed over the gate electrode. A selective etch and deposition process is performed to form a dielectric protection layer on the gate capping layer while forming a contact opening within the lower ILD layer. A lower source/drain contact is formed within the contact opening.