MOL Interconnect Structure Combining Via and Line Levels
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Solution Overview
Problem
Current semiconductor technologies face challenges in reducing middle-of-line (MOL) resistance and capacitance, which are critical for further miniaturization and performance enhancement of semiconductor devices.
Innovation Solution
The implementation of a semiconductor structure that incorporates a dual-damascene plus subtractive etching technique to form interconnects, featuring a damascene portion and a subtractive portion made of the same metal, with the subtractive portion increasing in width from top to bottom and the damascene portion decreasing in width, thereby reducing the number of via and line levels, resulting in lower resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interconnect structures with multiple via and line levels are used, then device complexity is reduced, but resistance and capacitance increase
Solution Approach 1:
The patent combines the via and line levels into a single integrated interconnect structure. The damascene portion forms via holes that directly connect to source/drain regions, while the subtractive portion forms contact lines on the same level, eliminating the need for separate via and line levels. This merging reduces the number of interfaces and thus reduces both resistance and capacitance.
Solution Approach 2:
The patent transitions from a multi-level vertical stacking approach to a planar integration approach within a single level. By using a dual-damascene process with selective metal deposition, the via and line functions are achieved in the same plane rather than requiring multiple stacked levels, reducing the vertical dimension complexity.
2Reliability
If the number of via and line levels is minimized, then resistance and capacitance decrease, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: first forming the damascene portion with via holes, then forming the subtractive portion with contact lines. This segmentation allows each portion to be optimized independently while maintaining overall integration, making the complex process more manageable and controllable.
Solution Approach 2:
The patent performs preliminary patterning and deposition steps to prepare the substrate for the dual-damascene process. The mandrel formation, spacer deposition, and selective etching are performed in advance to create the precise geometry needed for the final interconnect structure, ensuring manufacturability despite the process complexity.
Data Source
AI summary
A semiconductor structure includes a plurality of vertical transport field effect transistors, and an interconnect structure connected to one of respective source/drain regions of at least two vertical transport field effect transistors of the plurality of vertical transport field effect transistors and respective gate regions of the at least two vertical transport field effect transistors. The interconnect structure comprises a damascene portion, and a subtractive portion disposed on the damascene portion.