MOL MIM Capacitor Fabrication for 20 nm Precision
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Solution Overview
Problem
As technology scales down to 20 nm and beyond, the variation in metal wire thickness and width for finger metal oxide metal (Fmom) capacitors becomes severe, making it challenging to fabricate small value capacitance in integrated circuit devices, and the use of metal-insulator-metal (MIM) capacitors in back end of line (BEOL) layers requires additional masks and a high-K oxide deposition process.
Innovation Solution
A method for fabricating a metal-insulator-metal (MIM) capacitor using middle of line (MOL) conductive layers, where a first MOL conductive layer provides a capacitor plate and local interconnects, and a second MOL conductive layer forms the second plate, with an insulator layer acting as the dielectric, allowing for capacitance determination by dielectric thickness without additional masks or layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If Fmom capacitors are used in current process technology (28 nm), then fabrication is feasible, but severe variation in metal wire thickness and width results in severe capacitance variation
Solution Approach 1:
The patent transitions from planar Fmom capacitor geometry to a vertical MIM capacitor structure by stacking conductive layers separated by a dielectric layer. This dimensional change from 2D to 3D architecture enables precise capacitance control through dielectric thickness modulation rather than metal wire dimension control, directly addressing the variation problem at 28 nm and below
Solution Approach 2:
The invention changes the critical control parameter from metal wire width/thickness (in Fmom capacitors) to dielectric layer thickness (in MIM capacitors). By using atomic layer deposition (ALD) to precisely control the dielectric thickness at the nanometer scale, the patent achieves superior capacitance precision and reduced variation compared to controlling metal wire dimensions
2Productivity
If MIM capacitors are implemented in back end of line (BEOL) layers, then high capacitor density is achieved, but three additional masks and a high-K oxide deposition process are required
Solution Approach 1:
The patent merges the capacitor fabrication process with the existing MOL interconnect formation process. The first MOL conductive layer serves dual purposes as both an interconnect and the first capacitor plate, eliminating the need for separate capacitor electrode formation steps and reducing the number of additional masks required
Solution Approach 2:
The MOL conductive layers are designed to serve multiple functions: as local interconnects for semiconductor devices and as capacitor plates for MIM capacitors. This multi-functionality allows the same structural elements to fulfill both interconnection and energy storage roles, simplifying the overall fabrication process while maintaining high capacitor density
3Length of moving object
If technology scales down to 20 nm and beyond, then device miniaturization is achieved, but Fmom capacitors are no longer feasible for providing small value capacitance
Solution Approach 1:
As device dimensions scale down to 20 nm and below, the patent employs vertical stacking of MIM capacitor structures to achieve the required capacitance values. This vertical dimension compensates for the reduced horizontal dimensions, maintaining fabrication feasibility while enabling device miniaturization
Solution Approach 2:
The invention changes the scaling approach by controlling dielectric thickness through atomic layer deposition rather than scaling metal wire dimensions. This parameter change enables precise capacitance control at 20 nm and below where metal wire variation becomes uncontrollable, maintaining ease of manufacture despite aggressive scaling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of MIM capacitors using existing MOL interconnect layers and conductive resistor layers, achieving high density capacitance values with reduced complexity and cost, suitable for advanced process technologies like 20 nm and beyond.
Implementation Method 1
depositing an insulator layer on the first MOL conductive layer as a dielectric layer of the capacitor
Data Source
AI summary
A method for fabricating a metal-insulator-metal (MIM) capacitor includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first plate of the MIM capacitor as well as a first set of local interconnects to source and drain regions of a semiconductor device. The method also includes depositing an insulator layer on the first MOL conductive layer as a dielectric layer of the MIM capacitor. The method further includes depositing a second MOL conductive layer on the insulator layer as a second plate of the MIM capacitor.