MOL Shielded Gate Structure for Lower MOSFET Drain Capacitance
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Solution Overview
Problem
Existing methods for fabricating shielded gate MOSFETs in integrated circuits (ICs) require additional polysilicon deposition, mask, and etch steps, which increase costs, complexity, and the risk of defects.
Innovation Solution
The implementation of a middle-of-line (MOL) shielded gate in ICs, where one or more metal resistors are fabricated in the MOL layer to shield semiconductor devices, reducing gate-to-drain capacitance without the need for additional fabrication steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a WSi Faraday shield is fabricated between the gate and the underlying drain, then gate-to-drain capacitance is reduced, but fabrication complexity and cost increase due to additional polysilicon deposition, mask, and etch steps
Solution Approach 1:
The patent merges the Faraday shield function with the existing middle-of-line (MOL) resistor structure. By forming the Faraday shield using the same polysilicon deposition, mask, and etch processes already required for creating MOL resistors, the invention eliminates the need for separate additional fabrication steps. The MOL resistor and Faraday shield share common fabrication pathways, thereby reducing overall process complexity while maintaining effective gate-to-drain capacitance reduction.
Solution Approach 2:
The patent makes the MOL layer structure serve multiple functions: it acts as both a resistor element for RF grounding and as a Faraday shield for electric field shielding. The polysilicon structure in the MOL layer simultaneously provides resistance functionality and capacitance reduction, eliminating the need for dedicated single-function structures and simplifying the overall fabrication process.
2Object-affected harmful factors
If a WSi Faraday shield is fabricated between the gate and the underlying drain, then gate-to-drain capacitance is reduced, but manufacturing cost increases due to additional process steps
Solution Approach 1:
The patent combines the Faraday shield fabrication with the existing MOL resistor fabrication process flow. Since both structures require polysilicon deposition, masking, and etching, the invention utilizes the same process steps for both, thereby avoiding additional manufacturing costs associated with separate fabrication sequences.
Solution Approach 2:
The MOL resistor structure automatically provides Faraday shield functionality as part of its inherent design. The same polysilicon material and structural configuration that creates the resistor also creates the shielding effect, allowing the structure to serve itself for multiple purposes without requiring additional dedicated components or processes.
3Object-affected harmful factors
If a WSi Faraday shield is fabricated between the gate and the underlying drain, then gate-to-drain capacitance is reduced, but defect risk increases due to additional fabrication steps
Solution Approach 1:
The patent integrates Faraday shield fabrication into the existing MOL resistor process flow, thereby reducing the total number of discrete fabrication steps. By using the same polysilicon deposition, mask, and etch processes for both MOL resistors and Faraday shields, the invention minimizes the cumulative defect risk that would arise from multiple separate process sequences.
Solution Approach 2:
The Faraday shield structure is formed as part of the preliminary MOL layer fabrication process, before subsequent interconnect and metallization layers are added. By establishing the shielding functionality early in the process flow using already-planned process steps, the invention avoids introducing additional defect opportunities in later fabrication stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate-to-drain parasitic capacitance while minimizing additional fabrication costs and complexity, thereby enhancing the performance and reliability of ICs.
Implementation Method 1
reducing gate-to-drain parasitic capacitance
Data Source
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Figure 3A
AI summary
Middle-of-line (MOL) shielded gate in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC to reduce gate to drain parasitic capacitance in the semiconductor area. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized close to semiconductor devices to more effectively reduce parasitic capacitance of the semiconductor devices without adding costs or defects to the current fabrication processes. The current fabrication processes may be used to create contacts in the MOL to fabricate the metal resistor.