Mold-Embedded Traces for Fan-Out Wafer Level Packages
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Solution Overview
Problem
Fan-Out Wafer Level Packaging processes face challenges with increased redistribution layer counts and wiring densities, leading to higher package height, complexity, and the likelihood of delamination, while aiming to interconnect multiple microelectronic components efficiently.
Innovation Solution
Incorporating mold-embedded electrically-conductive traces, such as printed ink traces, within the molded package body, which are printed directly onto semiconductor die and microelectronic components before encapsulation, allowing for three-dimensional wiring and reducing the need for complex redistribution layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple microelectronic components are interconnected using traditional redistribution layers, then interconnectivity is achieved, but package height increases and fabrication complexity increases
Solution Approach 1:
The patent transitions from planar redistribution layers to three-dimensional mold-embedded traces. Conductive traces are formed within the molded package body, utilizing the vertical dimension and internal volume of the package. This allows interconnections to route through the package depth rather than requiring multiple stacked redistribution layers, thereby reducing package height and fabrication complexity while maintaining interconnectivity.
2Adaptability or versatility
If redistribution layer wiring density is increased to accommodate more interconnections, then interconnectivity is improved, but the likelihood of delamination increases
Solution Approach 1:
By embedding conductive traces within the molded package body rather than using planar redistribution layers, the patent eliminates the delamination risk associated with high-density stacked layers. The traces are integrated into the mold compound matrix, distributing mechanical stress uniformly and avoiding the interface between separate layered structures that are prone to delamination.
3Adaptability or versatility
If traditional redistribution layers are used to interconnect components, then electrical connections are established, but package size increases
Solution Approach 1:
The patent embeds conductive traces within the molded package body, nesting the interconnection structure inside the package volume rather than adding external redistribution layers. This utilizes the internal space of the package efficiently, allowing traces to be contained within the mold compound without increasing the overall package footprint or height.
Data Source
AI summary
Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.