Circuit Board Structure With Mold-Layer Recesses for Chip Alignment
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Solution Overview
Problem
Existing circuit board manufacturing methods face challenges in efficiently embedding chips due to space consumption by copper pads, difficulty in controlling recess depth, substrate warping, and alignment issues during chip insertion.
Innovation Solution
A method involving a mold layer with recesses to form insulating layers with bumps, allowing precise control of recess shapes and depths, and using bumps for alignment, reducing manufacturing costs and chip damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If copper pads are used to control recess depth, then the recess depth can be controlled, but a lot of space is consumed in the layout
Solution Approach 1:
The patent removes the copper pad from the system by using a mold layer with recesses to define the chip insertion space. The mold layer's recess profile directly determines the insertion space geometry, eliminating the need for separate copper pad structures while maintaining depth control precision.
Solution Approach 2:
The mold layer's recess profile is transferred to the insulating layer to form the chip insertion space. This copying mechanism allows the recess shape and depth to be defined by the mold layer geometry rather than requiring additional copper pad structures, reducing space consumption.
2Ease of manufacture
If laser processing is performed directly above the copper pad to form chip placement recess, then the recess can be formed for subsequent chip insertion, but it is difficult to control the processing depth without special inductive function
Solution Approach 1:
The mold layer with pre-formed recesses is created before forming the insulating layer. This preliminary action defines the exact recess profile and depth that will be transferred to the final structure, eliminating the need for complex real-time depth control during laser processing.
Solution Approach 2:
The mold layer acts as an intermediary that defines the recess geometry. Instead of directly controlling laser depth through complex induction systems, the mold layer's physical recess profile serves as a template that is transferred to the insulating layer, simplifying the manufacturing process.
3Manufacturing precision
If a release film is used to control the depth of chip insertion space, then the depth can be controlled, but the substrate may warp at the spot where the release film is peeled off
Solution Approach 1:
The patent eliminates the release film from the system by using a mold layer with recesses that directly define the insertion space. This removal of the release film prevents the substrate warping issue that occurs during film peeling, while maintaining depth control through the mold layer's recess profile.
4Stability of the object's composition
If support plate is introduced to overcome substrate warping, then warping can be prevented, but alignment problems during chip insertion still remain
Solution Approach 1:
The mold layer serves as an intermediary that simultaneously prevents substrate warping and provides alignment features. The bumps formed on the insulating layer from the mold layer's recesses act as alignment guides for chip insertion, eliminating the need for separate support plates while solving both problems.
5Adaptability or versatility
If the number of chips embedded in the carrier board is increased to meet product function requirements, then more functions can be achieved, but the limited space per unit area becomes a constraint
Solution Approach 1:
The patent changes the geometric parameters of the chip insertion spaces by using mold layers with varying recess profiles. This allows optimization of space utilization and accommodates different chip sizes and configurations, enabling more chips to be embedded in limited areas while maintaining manufacturing precision.
Data Source
AI summary
A circuit board structure is provided. The circuit board structure includes a first insulating layer, a second insulating layer, a vertical conductive feature, and an electronic element. The first insulating layer has multiple bumps thereon. The second insulating layer is disposed on the first insulating layer. The vertical conductive feature includes a first via hole and a second via hole extending vertically in the first insulating layer. The electronic element is disposed in the second insulating layer and surrounded by the bumps. The electronic element is electrically connected to the first via hole.