Mold Via Sidewall Roughness in Semiconductor Packages to Prevent Delamination
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Solution Overview
Problem
Existing semiconductor packages face challenges in reliability and yield due to delamination issues between mold layers and vias, which are exacerbated by smooth sidewalls that provide insufficient adhesive force.
Innovation Solution
The semiconductor package design incorporates mold vias with non-aligned sidewalls and increased surface roughness, particularly on the upper sidewall, to enhance adhesive force and prevent delamination, using a method that includes forming photoresist layers and performing roughness formation processes on the sidewalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the mold via has smooth sidewalls, then the manufacturing process is simple, but the adhesive force between mold layer and via is insufficient causing delamination
Solution Approach 1:
The patent applies parameter changes by modifying the surface roughness parameter of the mold via sidewalls. Specifically, the upper sidewall is designed with increased surface roughness compared to the lower sidewall, creating different adhesion characteristics at different heights. This parameter modification enables the mold layer to firmly adhere to the via structure without requiring complete redesign of the manufacturing process.
Solution Approach 2:
The patent implements local quality by creating non-uniform surface characteristics on different parts of the via structure. The upper sidewall possesses different surface properties (higher roughness) than the lower sidewall, allowing each region to serve its specific function: the upper region provides enhanced adhesion for the mold layer, while the lower region maintains structural integrity and electrical connection functionality.
2Reliability
If the upper sidewall surface roughness is increased, then the adhesion between mold layer and via is enhanced, but the manufacturing complexity increases
Solution Approach 1:
The patent applies partial action by selectively increasing surface roughness only on the upper sidewall region where adhesion is most critical for preventing delamination, rather than uniformly roughening the entire via structure. This targeted approach provides sufficient adhesion enhancement while minimizing the complexity added to the manufacturing process.
3Reliability
If the middle sidewall is not aligned with upper or lower sidewalls, then the adhesion area is increased, but the manufacturing precision requirement increases
Solution Approach 1:
The patent applies parameter changes by intentionally introducing misalignment between the middle sidewall and the upper/lower sidewalls. This controlled imperfection increases the effective adhesion area between the mold layer and via structure, while the misalignment parameters are designed to be within manufacturable tolerances.
Data Source
AI summary
Disclosed are semiconductor packages and their fabrication methods. The semiconductor package includes a first substrate, a semiconductor device on the first substrate, a mold layer that covers the first substrate and the semiconductor device, a second substrate on the mold layer, and a mold via that penetrates the mold layer and connects the first substrate to the second substrate. The mold via has an upper sidewall and a lower sidewall. A surface roughness of the upper sidewall is greater than a surface roughness of the lower sidewall.