Molded Array Package with Exposed Tab for Thermal Management

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Solution Overview

Problem

Conventional chip scale packaging technologies, such as QFP, QFN, and DFN, face challenges in heat transfer capability for high power applications and limited mounting options for attaching packages to next levels of assembly like heat sinks and printed circuit boards.

Innovation Solution

The development of a molded array package with exposed tabs and through-holes, which allows for improved heat transfer and flexible attachment options using lead frames compatible with existing chip scale assembly platforms, enabling better thermal management and diverse mounting configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If conventional QFP, QFN, or DFN packages are used, then the package size is minimized close to chip size, but heat transfer capability is poor for high power applications

Engineering Contradiction:
Improveheat transfer capabilityVSAvoidmounting options
Core Design Contradiction:
TemperatureVSAdaptability or versatility

Solution Approach 1:

The package structure is segmented into distinct functional zones: a large bottom surface area for thermal attachment to heat sinks, peripheral leads for electrical connection, and an exposed tab for mechanical mounting. This segmentation allows each area to optimize its function independently, resolving the contradiction between heat transfer and mounting versatility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention utilizes the vertical dimension by exposing the tab on the top surface of the mold compound rather than confining all connections to the bottom plane. This dimensional change enables through-hole mounting and vertical heat path integration, simultaneously improving heat transfer capability and mounting flexibility without increasing footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If conventional QFP, QFN, or DFN packages are used, then chip scale packaging is achieved, but mounting options for attaching to heat sinks and PCBs are limited

Engineering Contradiction:
Improvemounting optionsVSAvoidpackage structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The exposed tab serves multiple functions simultaneously: it provides mechanical support for mounting to PCBs and heat sinks, acts as a thermal conduction path, and enables through-hole attachment methods. This multi-functionality increases adaptability without proportionally increasing structural complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The lead frame is nested within the mold compound, with the exposed tab emerging through the mold surface. This nested configuration allows the package to maintain a compact form factor while providing external mounting interfaces, balancing versatility with structural simplicity.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Temperature

If conventional packages are used, then automated assembly is simplified, but heat transfer capability deteriorates

Engineering Contradiction:
Improveheat transfer capabilityVSAvoidassembly process
Core Design Contradiction:
TemperatureVSEase of manufacture

Solution Approach 1:

The tab is pre-formed as an integral part of the lead frame structure before packaging, with through-holes already positioned and sized for standard mounting operations. This preliminary preparation enables straightforward automated assembly while establishing optimized thermal pathways from the chip through the tab to external heat sinks.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7602054B2Method of forming a molded array package device having an exposed tab and structure
Publication Date: 2009.10.13 SEMICON COMPONENTS IND LLC
  • US7602054B2 patent drawing
  • US7602054B2 patent drawing
  • US7602054B2 patent drawing

AI summary

In one embodiment, a method for forming a molded flat pack style package includes attaching electronic chips to an array lead frame, which includes a plurality of elongated flag portions with tab portions and a plurality of leads. The method further includes connecting the electronic chips to specific leads, and then molding the array lead frame while leaving portions of the leads exposed to form a molded array structure. The molded array structure is then separated to provide molded flat pack style packages having exposed leads for insertion mount and exposed tab portions. In an alternative embodiment, the separation step produces a no-lead configuration with exposed tab portions.