Molded Die Package with Redistribution Structure

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In semiconductor packaging, the miniaturization of electronic products has led to challenges in heat dissipation and data transmission speed, particularly for multi-die packages, where the arrangement of dies and connecting elements affects reliability and performance.

Innovation Solution

A method involving the use of a carrier with a de-bonding layer, seed material layers, and micro-bumps to bond and encapsulate semiconductor dies, followed by a planarization process to achieve uniform thickness and improve electrical connections through redistribution structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If semiconductor dies are packaged in multi-die configuration, then functionality and integration are improved, but heat dissipation becomes more difficult and reliability decreases

Engineering Contradiction:

ImproveintegrationVSAvoidheat dissipation

Core Design Contradiction:

Adaptability or versatilityVSTemperature

Solution Approach 1:

The patent transitions from traditional planar packaging to three-dimensional stacked packaging, where semiconductor dies are arranged vertically in multiple layers and connected through vias. This dimensional change allows better heat distribution across multiple surfaces and improves integration density while managing thermal challenges through vertical architecture.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent applies different material properties to different regions of the package: thermally conductive materials are used in heat dissipation structures, while electrically insulating but thermally conductive materials are used in interlayer dielectrics. This localized material selection optimizes both heat dissipation and electrical performance in specific areas.

Inventive Principle:

Principle #3Local quality

2Speed

If connecting elements are added for multi-die packages, then data transmission speed is improved, but manufacturing complexity and reliability risks increase

Engineering Contradiction:

Improvedata transmission speedVSAvoidarrangement of dies and connecting elements

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent forms conductive vias and interlayer dielectric structures before stacking the semiconductor dies. This preliminary preparation of connection pathways simplifies the subsequent stacking process and ensures proper alignment, reducing manufacturing complexity while enabling high-speed data transmission through pre-established electrical connections.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent designs the interlayer dielectric structure to serve multiple functions: providing electrical insulation between conductive layers, offering mechanical support for stacked dies, and facilitating heat dissipation. This multi-functionality reduces the need for separate dedicated structures, simplifying overall device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Manufacturing precision

If planarization process is applied to achieve uniform thickness, then manufacturing precision is improved, but process complexity increases

Engineering Contradiction:

Improveuniform thicknessVSAvoidplanarization process

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent performs planarization of the substrate and forms a uniform base layer before stacking semiconductor dies. This preliminary planarization ensures that subsequent die stacking occurs on a flat surface, achieving uniform overall thickness without requiring complex post-assembly planarization processes.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent encapsulates multiple semiconductor dies within a single molded package structure, where each die is nested within the same protective encapsulant. This nesting approach achieves uniform external dimensions and thickness while protecting the internal multi-die architecture, simplifying the overall manufacturing process.

Inventive Principle:

Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances heat dissipation, data transmission speed, and reliability by ensuring uniform thickness and efficient electrical connectivity among semiconductor dies in packaged products.

Implementation Method 1

In some embodiments, the de-bonding layer 102 includes a light-to-heat conversion (LTHC) release layer, which facilitates peeling the carrier 100 away when required by the manufacturing process.

Methodology Applied

Scientific EffectLight-to-heat conversion:

Data Source

PatentUS11538761B2Semiconductor package having molded die and semiconductor die and manufacturing method thereof

Publication Date: 2022.12.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor package includes a first semiconductor die, a molded die, a third encapsulant, and a redistribution structure. The molded die includes a chip, a first encapsulant, and a second encapsulant. The first encapsulant laterally wraps the chip. The second encapsulant laterally wraps the first encapsulant. The third encapsulant laterally wraps the first semiconductor die and the molded die. The redistribution structure extends on the second encapsulant, the third encapsulant, and the first semiconductor die. The redistribution structure is electrically connected to the first semiconductor die and the molded die. The second encapsulant separates the first encapsulant from the third encapsulant.