Molded Interposer Embedding Passive Devices for Compact Wafer Level Packages
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Solution Overview
Problem
Conventional 2.5D semiconductor packages with TSV silicon interposers are costly and have a larger surface area due to the complexity of fabricating TSV interposers and the placement of passive devices, making it undesirable for certain applications and requiring a smaller form factor.
Innovation Solution
A molded interposer with a layer of first molding compound, redistribution layers, metal vias for electrical connection, and embedded passive devices, where the passive devices are electrically connected to the redistribution layers, allowing for a smaller size and reduced surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV silicon interposer is used to integrate multiple chips, then higher density interconnects and enhanced performance are achieved, but the fabrication process becomes complex and costly
Solution Approach 1:
The patent replaces expensive TSV silicon interposers with organic substrate interposers that are cheaper to fabricate. The organic substrate serves as a disposable interposer that achieves the same interconnect function without requiring complex TSV fabrication processes, thereby reducing both cost and manufacturing complexity while maintaining interconnect density
Solution Approach 2:
The patent changes the material parameter of the interposer from silicon to organic substrate materials. This parameter change fundamentally alters the fabrication approach, eliminating the need for TSV processes and enabling simpler, more cost-effective manufacturing while preserving the electrical interconnect functionality
2Adaptability or versatility
If passive devices are mounted on the same surface as dies on TSV interposer, then integration is achieved, but the interposer surface area increases
Solution Approach 1:
The patent utilizes the vertical dimension by embedding passive devices within the organic substrate interposer rather than mounting them on the surface. This dimensional transition from 2D surface mounting to 3D embedded placement allows passive devices to coexist with dies on the same interposer without increasing the horizontal surface area, achieving high integration in a compact footprint
3Reliability
If TSV interposer is used for wafer level package, then performance is enhanced, but the package size becomes larger
Solution Approach 1:
The patent replaces bulky TSV silicon interposers with thinner organic substrate interposers that provide the same performance benefits. The organic substrate enables wafer-level packaging with reduced thickness and smaller overall package volume while maintaining the enhanced performance characteristics through alternative interconnect methodologies
Data Source
AI summary
Semiconductor packages may include a molded interposer and semiconductor dice mounted on the molded interposer. The molded interposer may include two redistribution layer structures on opposite sides of a molding compound. Electrically conductive vias may connect the RDL structures through the molding compound, and passive devices may be embedded in the molding compound and electrically connected to one of the RDL structures. Each of the semiconductor dice may be electrically connected to, and have a footprint covering, a corresponding one of the passive devices to form a face-to-face connection between each of the semiconductor dice and the corresponding one of the passive devices.