Molded Multi-Chip Package Structure for Faster Signal Routing
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, the complexity of fabrication processes increases, making it challenging to form reliable semiconductor devices at smaller scales.
Innovation Solution
The development of a chip package structure that includes a redistribution structure with a dielectric structure and wiring structure, along with conductive pillars and molding layers, to facilitate efficient electrical connections and support the integration of multiple chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity increases and reliability decreases
Solution Approach 1:
The chip package structure is divided into multiple functional layers including die, molding layer, substrate, and wiring structures. This segmentation allows each layer to be optimized independently for its specific function while maintaining overall system reliability, addressing the complexity issue by breaking down the fabrication process into manageable stages.
Solution Approach 2:
The patent transitions from planar 2D chip layouts to three-dimensional packaging structures with multiple stacking layers. By utilizing the vertical dimension, the design achieves higher functional density without proportionally increasing lateral fabrication complexity, as the additional complexity is confined to vertical integration rather than expanding the fabrication footprint.
2Quantity of substance
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but manufacturing reliability decreases
Solution Approach 1:
The molding layer is positioned between the die and the external environment to provide mechanical protection and stress distribution before failure can occur. This cushioning layer compensates for the reduced margin for error in smaller features by providing a buffer that protects critical semiconductor structures from external stresses and defects.
Solution Approach 2:
The chip package employs composite material structures combining different materials with complementary properties - the die provides active functionality, the molding layer provides mechanical protection and insulation, and the substrate provides structural support. This composite approach ensures that the weaknesses of miniaturized features are compensated by the strengths of surrounding materials.
3Ease of manufacture
If traditional chip package structures are used, then manufacturing is simpler, but signal transmission speed is slower and overall thickness is larger
Solution Approach 1:
The patent implements vertical stacking of functional layers to reduce the horizontal distance for signal transmission. By routing signals through the vertical dimension via conductive pillars and wiring structures, the design achieves faster signal transmission without requiring complex lateral interconnections, thus maintaining manufacturing feasibility while improving performance.
Solution Approach 2:
The substrate acts as an intermediary structure that provides optimized signal pathways between the die and external connections. This intermediate layer includes controlled impedance wiring and transmission lines that enhance signal speed and integrity, bridging the gap between simple manufacturing requirements and high-performance signal transmission needs.
4Ease of manufacture
If traditional chip package structures are used, then manufacturing is simpler, but overall thickness is larger
Solution Approach 1:
The patent utilizes vertical stacking to consolidate multiple functional elements into a compact three-dimensional structure. By arranging the die, molding layer, substrate, and wiring structures in vertical layers, the design reduces the horizontal footprint while maintaining necessary functional thickness, achieving a more space-efficient package that is easier to manufacture than traditional lateral expansion designs.
Data Source
AI summary
A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip over the first surface. The chip package structure includes a second chip over the second surface. The chip package structure includes a conductive pillar over the second surface and adjacent to the second chip. The chip package structure includes a molding layer over the second surface and surrounding the second chip. The chip package structure includes a second redistribution structure over the second chip. The chip package structure includes a buffer layer between the second redistribution structure and the second chip. The chip package structure includes a third chip over the second redistribution structure.