Molded Semiconductor Package Layout for Sidewall Contact Redirection
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Solution Overview
Problem
The fabrication of packaged semiconductor devices with vertical interconnects increases processing time and cost, necessitating improved methods and devices for efficient electrical contact redirection across opposing sides.
Innovation Solution
A method involving arranging semiconductor dies in an array with conductive elements laterally positioned between them, molding to form a packaged device, and singulating to create devices with a redistribution layer and conductive elements extending from the first side to the second side, reducing fabrication complexity and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If vertical interconnects are added to redirect electrical contacts to opposing sides, then device functionality and stacking capability are improved, but fabrication time and cost increase
Solution Approach 1:
The conductive elements are arranged laterally besides the semiconductor dies during the initial array formation stage, before molding. This preliminary positioning allows vertical interconnect functionality to be established without requiring additional processing steps after packaging, thereby reducing fabrication time while maintaining device functionality
Solution Approach 2:
The invention combines the lateral arrangement of conductive elements with the molding process into a single integrated fabrication step. By arranging conductive elements on the same substrate as semiconductor dies and molding them together, the patent merges multiple operations (element placement, substrate attachment, encapsulation) into one cohesive process, eliminating sequential processing steps that would increase fabrication time
2Adaptability or versatility
If vertical interconnects are added to redirect electrical contacts, then stacking capability is improved, but fabrication complexity increases
Solution Approach 1:
Conductive elements are positioned laterally besides semiconductor dies during the initial array configuration, establishing vertical interconnect pathways before the molding process begins. This preliminary arrangement simplifies subsequent fabrication steps by pre-defining interconnect locations and eliminating the need for complex post-packaging processing
Solution Approach 2:
The lateral conductive elements serve as intermediary structures that bridge the semiconductor die and the molding process. These elements are arranged on the same substrate as the dies and are encapsulated together, providing a simplified interface for creating vertical interconnects without requiring complex additional processing steps
3Adaptability or versatility
If vertical interconnects are added to redirect electrical contacts, then device adaptability is improved, but fabrication cost increases
Solution Approach 1:
The invention merges the arrangement of conductive elements with the semiconductor die array formation and molding process into a single integrated fabrication step. By combining these operations that would traditionally be performed sequentially into one cohesive process, the patent eliminates multiple processing steps, reduces manufacturing complexity, and lowers fabrication costs while maintaining device adaptability
Solution Approach 2:
Conductive elements are positioned laterally during the initial array formation stage, establishing vertical interconnect functionality before molding. This preliminary positioning eliminates the need for additional post-packaging processing steps, thereby reducing fabrication costs while maintaining the ability to redirect electrical contacts for stacking applications
Data Source
AI summary
A method for fabricating packaged semiconductor devices is disclosed. In one example the method comprises providing a plurality of semiconductor dies, the semiconductor dies being arranged in an array on a carrier such that a first side of the semiconductor dies faces the carrier and such that an empty space is arranged laterally besides each semiconductor die. A substrate comprising a plurality of conductive elements is arranged over the plurality of semiconductor dies such that a conductive element is arranged in the respective empty space besides each one of the semiconductor dies. The plurality of semiconductor dies are molded over to form a molded body, and singulating packaged semiconductor devices from the molded body by cutting through the molded body.