Molded Power Electronics Module with Height-Controlled Spacers
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Solution Overview
Problem
Power semiconductor chips in high power applications generate significant heat, requiring efficient thermal dissipation and reliable packaging that also provides mechanical support and electrical interconnections, but existing solutions struggle to balance these demands effectively.
Innovation Solution
A power electronic package design featuring spacers between substrates to control height variation, reduce mechanical stress, and enhance thermal dissipation, with spacer heights determined by chip and solder block dimensions to maintain a precise height variation of less than 0.1 mm, and using a fully molded structure with encapsulants for improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If power semiconductor chips are built into packages for high power applications, then thermal dissipation capability is improved, but mechanical stress and reliability issues worsen
Solution Approach 1:
The package structure is segmented into multiple functional layers including substrate, spacer, molding compound, and solder blocks. This segmentation allows each component to independently optimize its function - the substrate handles thermal dissipation, the spacer provides mechanical support and stress relief, and the molding compound protects internal structures, thereby resolving the contradiction between thermal performance and mechanical reliability
Solution Approach 2:
A spacer is introduced as an intermediary component between the substrate and molding compound. This spacer acts as a mediator that provides mechanical support, controls height variation, and relieves stress on solder blocks and chips, enabling the package to simultaneously achieve good thermal dissipation through the substrate while maintaining mechanical reliability through the spacer's stress-distributing function
2Manufacturing precision
If spacer height is precisely controlled based on chip and solder block dimensions, then height variation is reduced to less than 0.1 mm, but manufacturing complexity increases
Solution Approach 1:
The spacer height is predetermined based on the dimensions of chips and solder blocks before assembly. By calculating and setting the spacer height in advance according to the formula H = h1 + h2 + h3 (where H is spacer height, h1 is chip height, h2 is top solder block height, and h3 is bottom solder block height), the package achieves precise height control of less than 0.1 mm variation without requiring complex real-time adjustments during manufacturing
Solution Approach 2:
The spacer height parameter is optimized based on specific chip and solder block dimensions. By changing the spacer height parameter according to the actual components used, the package achieves precise height control while maintaining manufacturing feasibility. The parameter is calculated as H = h1 + h2 + h3, allowing flexible adaptation to different component sizes while keeping height variation below 0.1 mm
3Reliability
If fully molded structure with encapsulants is used, then reliability is improved, but parasitic inductance and resistance increase
Solution Approach 1:
The molding compound is selectively applied to protect internal structures while leaving critical electrical pathways exposed or minimally covered. This local quality approach ensures that areas requiring mechanical protection and environmental sealing are fully molded, while electrical connection areas maintain low parasitic inductance and resistance, thus resolving the contradiction between reliability improvement and harmful factor reduction
Data Source
AI summary
A power electronic package includes a first substrate, a second substrate oppositely disposed from the first substrate, one or more chips disposed between the substrates, and at least three spacers. The spacers control a height variation of the power electronic package and protect the chips and other electronics from experiencing excessive stress. The height of the spacers is determined based on a height of the chips, on a height of solder blocks that connect the chips to the top substrate, and on a height of solder blocks that connect the chips to the bottom substrate.