Molded Reconfigured Wafer for High-Speed Stack Package
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional stack packages using metal wires suffer from slow signal exchange speed and increased package size due to the use of metal wires, while those using through-silicon vias have complex manufacturing processes and high costs, limiting miniaturization and increasing processing costs.
Innovation Solution
A molded reconfigured wafer with a molding part surrounding semiconductor chips, through-electrodes formed in the molding part, and re-distribution lines connecting the through-electrodes and bonding pads, allowing for the stacking of package units with good-quality semiconductor chips without the need for designing through-silicon vias, simplifying the manufacturing process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If metal wires are used for electrical connections in stack packages, then the package can be manufactured with simple processes, but the signal exchange speed is slow and the package size increases
Solution Approach 1:
The patent replaces metal wire bonding (mechanical connection) with direct through-electrode penetration through the semiconductor chip. This substitution eliminates the need for external wire connections and achieves faster electrical signal transmission while maintaining manufacturing feasibility through standardized through-electrode formation processes.
2Ease of manufacture
If metal wires are used for electrical connections, then the manufacturing process remains simple, but the package size increases due to additional area requirements
Solution Approach 1:
The patent extracts the electrical connection function from the external metal wire bonding process and integrates it directly into the semiconductor chip structure through through-electrodes. This extraction eliminates the need for additional substrate area to accommodate wire bonds and bonding pads, thereby reducing the overall package size while maintaining manufacturing simplicity.
3Speed
If through-silicon vias are used to improve signal exchange speed, then the operating speed increases, but the manufacturing process becomes complicated and costs increase
Solution Approach 1:
The patent segments the electrical connection function into two parts: through-electrodes formed during standard chip manufacturing (similar to through-silicon vias) and re-distribution lines formed on the chip surface. This segmentation allows the use of conventional chip manufacturing processes to create through-electrodes, avoiding the need for complex post-manufacturing modifications while achieving fast signal transmission.
4Speed
If through-silicon vias are formed to pass through semiconductor chips, then signal exchange speed improves, but the manufacturing cost increases due to wafer redesign requirements
Solution Approach 1:
The patent performs the through-electrode formation action during the standard semiconductor chip manufacturing process, before the chip is completed and packaged. This preliminary action integrates the through-electrode creation into existing manufacturing flows, eliminating the need for separate wafer redesign and re-fabrication steps, thereby reducing manufacturing costs while achieving fast signal transmission.
5Volume of moving object
If through-silicon vias are used, then miniaturization is enabled, but the manufacturing process complexity increases
Solution Approach 1:
The patent merges the through-electrode formation process with the standard semiconductor chip manufacturing process. By combining these functions into a single integrated process flow, the patent achieves miniaturization benefits without adding separate complex manufacturing steps, thereby reducing overall process complexity while enabling compact package design.
Data Source
AI summary
A stack package includes at least two stacked package units. Each package unit comprises semiconductor chips having bonding pads on upper surfaces thereof; a molding part formed to surround side surfaces of the semiconductor chips; through-electrodes formed in the molding part; and re-distribution lines formed to connect the through-electrodes and adjacent bonding pads with each other.