Stackable fully molded semiconductor structure with vertical interconnects
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in producing smaller semiconductor devices with higher density and efficiency, particularly in achieving smaller form factors and efficient packaging for wearable electronics and portable devices, due to limitations in front-end and back-end manufacturing processes.
Innovation Solution
A method involving the use of a carrier with a planar conductive seed layer, multiple photoresist layers, and copper posts to form conductive redistribution layers and encapsulate semiconductor dies with a mold compound, enabling vertical interconnects for package-on-package stacking and reducing device height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor packaging processes are used, then manufacturing simplicity is maintained, but device size and form factor cannot be sufficiently reduced
Solution Approach 1:
The patent implements vertical interconnects that extend through the mold compound from the top surface to the bottom surface, enabling three-dimensional packaging arrangements. This vertical dimension allows multiple semiconductor dies to be stacked or arranged in compact configurations, significantly reducing the horizontal footprint and overall device size while maintaining functional density.
Solution Approach 2:
The packaging process is divided into distinct stages: forming the mold compound, creating vertical interconnect channels, filling with conductive material, and subsequent die attachment. This segmentation allows each process step to be optimized independently and enables the integration of complex interconnect structures without proportionally increasing overall process difficulty.
2Productivity
If traditional interconnection methods are used, then manufacturing process simplicity is maintained, but electrical interconnection efficiency and density are insufficient
Solution Approach 1:
The patent transitions from planar, two-dimensional interconnection patterns to three-dimensional vertical interconnects that penetrate through the mold compound. This enables multiple electrical connections to be established in the vertical direction, significantly increasing interconnection density and efficiency without requiring proportionally larger device areas.
Solution Approach 2:
The mold compound serves as an intermediary medium that contains embedded vertical interconnects. These interconnects act as mediators between different electrical layers or dies, providing efficient electrical pathways through the insulation material and enabling dense interconnection architectures that would be impossible with traditional surface-mounted connections.
3Area of moving object
If larger device footprints are used, then manufacturing and packaging simplicity is maintained, but form factor reduction for wearable and portable devices is prevented
Solution Approach 1:
The patent utilizes vertical channels extending through the mold compound to create interconnects that occupy minimal horizontal space. This three-dimensional approach allows multiple connections to be packed into a small footprint area, enabling compact device designs suitable for wearable and portable applications while maintaining manufacturability through standardized vertical etching and filling processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of smaller, more efficient semiconductor devices with enhanced electrical interconnection and packaging, facilitating the production of smaller form factor devices suitable for wearable electronics and portable devices.
Implementation Method 1
The first photoresist layer is patterned to form first openings through the first photoresist that extend to the planar conductive seed layer. A second photoresist layer is formed over the first photoresist layer and the patterned first photoresist layer. The second photoresist layer is patterned to form second openings through the second photoresist that align with the first openings and extend to the non-planar conductive seed layer.
Implementation Method 2
Copper posts are plated over the non-planar conductive seed layer and within the first openings and the second openings.
Data Source
AI summary
A method of making a semiconductor device may include providing a carrier and forming a first photoresist over the carrier with first openings through the first photoresist. A non-planar conductive seed layer may be formed over the first photoresist and conformally extend into the first openings through the first photoresist. A second photoresist may be formed over the first photoresist and over the non-planar conductive seed layer. The second photoresist layer may be patterned to form second openings through the second photoresist that extend to the non-planar conductive seed layer. Conductive posts may be plated over the non-planar conductive seed layer and within the second openings. The second photoresist may be removed while leaving in place the first photoresist. A semiconductor die may be coupled to the carrier. The semiconductor die, the conductive posts, and the first photoresist may be encapsulated with mold compound.